cy7c453.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
--  File Name: cy7c453.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:  | mod date: | changes made:
--    V1.0     B.Bizic    01 Oct 02   Initial release
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    FIFO
--  Technology: CMOS
--  Part:       CY7C453
--
--  Description: Clocked FIFO with Programmable Flags 2,048 x 9
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cy7c453 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_ENWNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_ENRNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKW                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CKR                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_XINeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_MRNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_FLNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CKR_Q0                 : VitalDelayType01 := UnitDelay01;
        tpd_MRNeg_Q0             : VitalDelayType01 := UnitDelay01;-- tAMR
        tpd_MRNeg_ENeg          : VitalDelayType01 := UnitDelay01;-- tMEF
        tpd_CKW_ENeg             : VitalDelayType01 := UnitDelay01;
        tpd_OENeg_Q0             : VitalDelayType01Z := UnitDelay01Z;
        -- tpw values: pulse widths
        tpw_CKR_negedge          : VitalDelayType   := UnitDelay;
        tpw_CKR_posedge          : VitalDelayType   := UnitDelay;
        tpw_MRNeg_negedge        : VitalDelayType   := UnitDelay;
        tpw_FLNeg_negedge        : VitalDelayType   := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CKR              : VitalDelayType   := UnitDelay;
        -- tsetup values: setup times
        tsetup_D0_CKW            : VitalDelayType   := UnitDelay; --tSD
        tsetup_ENWNeg_CKW        : VitalDelayType   := UnitDelay; --tSEN
        tsetup_CKW_MRNeg         : VitalDelayType   := UnitDelay; --tSCMR
        -- thold values: hold times
        thold_D0_CKW             : VitalDelayType   := UnitDelay; --tHD
        thold_ENWNeg_CKW         : VitalDelayType   := UnitDelay; --tHEN

        -- tskew time:skew times 
        tdevice_SKEW1  : VitalDelayType := UnitDelay; -- tSKEW1
        tdevice_SKEW2  : VitalDelayType := UnitDelay; -- tSKEW2

        -- trecovery time:recovery time
        trecovery_CKW_MRNeg     : VitalDelayType := UnitDelay; -- tMRR
        trecovery_ENRNeg_FLNeg    : VitalDelayType := UnitDelay;

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        D0              : IN    STD_ULOGIC := 'U';
        D1              : IN    STD_ULOGIC := 'U';
        D2              : IN    STD_ULOGIC := 'U';
        D3              : IN    STD_ULOGIC := 'U';
        D4              : IN    STD_ULOGIC := 'U';
        D5              : IN    STD_ULOGIC := 'U';
        D6              : IN    STD_ULOGIC := 'U';
        D7              : IN    STD_ULOGIC := 'U';
        D8              : IN    STD_ULOGIC := 'U';
        Q0              : OUT   STD_ULOGIC := 'U';
        Q1              : OUT   STD_ULOGIC := 'U';
        Q2              : OUT   STD_ULOGIC := 'U';
        Q3              : OUT   STD_ULOGIC := 'U';
        Q4              : OUT   STD_ULOGIC := 'U';
        Q5              : OUT   STD_ULOGIC := 'U';
        Q6              : OUT   STD_ULOGIC := 'U';
        Q7              : OUT   STD_ULOGIC := 'U';
        Q8              : OUT   STD_ULOGIC := 'U';
        ENWNeg          : IN   STD_ULOGIC := 'U';
        ENRNeg          : IN   STD_ULOGIC := 'U';
        CKW             : IN   STD_ULOGIC := 'U';
        CKR             : IN   STD_ULOGIC := 'U';
        ENeg            : OUT   STD_ULOGIC := 'U';
        FLNeg           : IN    STD_ULOGIC := 'U';
        MRNeg           : IN    STD_ULOGIC := 'U';
        OENeg           : IN    STD_ULOGIC := 'U';
        XINeg           : IN    STD_ULOGIC := 'U';
        HFNeg           : OUT   STD_ULOGIC := 'U';
        XONeg           : OUT   STD_ULOGIC := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of cy7c453 : ENTITY IS TRUE;
END cy7c453;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of cy7c453 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "CY7C453";

    SIGNAL D0_ipd              : STD_ULOGIC := 'U';
    SIGNAL D1_ipd              : STD_ULOGIC := 'U';
    SIGNAL D2_ipd              : STD_ULOGIC := 'U';
    SIGNAL D3_ipd              : STD_ULOGIC := 'U';
    SIGNAL D4_ipd              : STD_ULOGIC := 'U';
    SIGNAL D5_ipd              : STD_ULOGIC := 'U';
    SIGNAL D6_ipd              : STD_ULOGIC := 'U';
    SIGNAL D7_ipd              : STD_ULOGIC := 'U';
    SIGNAL D8_ipd              : STD_ULOGIC := 'U';
    SIGNAL ENWNeg_ipd          : STD_ULOGIC := 'U';
    SIGNAL ENRNeg_ipd          : STD_ULOGIC := 'U';
    SIGNAL CKW_ipd             : STD_ULOGIC := 'U';
    SIGNAL CKR_ipd             : STD_ULOGIC := 'U';
    SIGNAL XINeg_ipd           : STD_ULOGIC := 'U';
    SIGNAL FLNeg_ipd           : STD_ULOGIC := 'U';
    SIGNAL MRNeg_ipd           : STD_ULOGIC := 'U';
    SIGNAL OENeg_ipd           : STD_ULOGIC := 'U';

    -- No Weak Values --
    SIGNAL D0_nwv              : STD_ULOGIC := 'U';
    SIGNAL D1_nwv              : STD_ULOGIC := 'U';
    SIGNAL D2_nwv              : STD_ULOGIC := 'U';
    SIGNAL D3_nwv              : STD_ULOGIC := 'U';
    SIGNAL D4_nwv              : STD_ULOGIC := 'U';
    SIGNAL D5_nwv              : STD_ULOGIC := 'U';
    SIGNAL D6_nwv              : STD_ULOGIC := 'U';
    SIGNAL D7_nwv              : STD_ULOGIC := 'U';
    SIGNAL D8_nwv              : STD_ULOGIC := 'U';
    SIGNAL ENWNeg_nwv          : STD_ULOGIC := 'U';
    SIGNAL ENRNeg_nwv          : STD_ULOGIC := 'U';
    SIGNAL CKW_nwv             : STD_ULOGIC := 'U';
    SIGNAL CKR_nwv             : STD_ULOGIC := 'U';
    SIGNAL XINeg_nwv           : STD_ULOGIC := 'U';
    SIGNAL FLNeg_nwv           : STD_ULOGIC := 'U';
    SIGNAL MRNeg_nwv           : STD_ULOGIC := 'U';
    SIGNAL OENeg_nwv           : STD_ULOGIC := 'U';
    
    -- FIFO memory definations
    CONSTANT FIFOSize       : POSITIVE  := 2048;
    CONSTANT FIFOWordLenght : POSITIVE  := 9;
    TYPE     FIFOArray     IS array (0 to FIFOSize) of INTEGER RANGE -2 TO 511;

    -- internal signals

    SIGNAL CountPointer     : NATURAL RANGE 0 TO FIFOSize :=0;
    SIGNAL ReadPointer      : NATURAL RANGE 0 TO FIFOSize :=0;
    SIGNAL WritePointer     : NATURAL RANGE 0 TO FIFOSize :=0;
    SIGNAL EmptyOffReg      : NATURAL:=16;
    SIGNAL FullOffReg       : NATURAL:=16;
    SIGNAL ProgReg          : STD_LOGIC_VECTOR(FIFOWordLenght - 1 DOWNTO 0)
    :="000000001";
    SIGNAL Start            : STD_ULOGIC := '0';
    SIGNAL parity_enable    : BOOLEAN:=FALSE;
    SIGNAL parity_odd_even  : STD_LOGIC;
    SIGNAL parity_generate  : BOOLEAN:=FALSE;

    -- SKEW stuff (see also generics list)

    ALIAS  tSKEW1          : VitalDelayType IS tdevice_SKEW1;
    ALIAS  tSKEW2          : VitalDelayType IS tdevice_SKEW2;
    SIGNAL tSKEW_CKW_CKR   : Time := 0 ns;    -- actual /CKW/CKR skew time
    SIGNAL tSKEW_CKR_CKW   : Time := 0 ns;    -- actual /CKR/CKW skew time
    SIGNAL OpenIn, OpenOut : STD_LOGIC;
    ALIAS  tCKR            : VitalDelayType IS tperiod_CKR;
    ALIAS  tCKW            : VitalDelayType IS tperiod_CKR;

BEGIN
--------------------------------------------------------------------------------
-- Dummy instances for exporting tSKEW vals from SDF file
-- using DEVICE construct
--------------------------------------------------------------------------------

  SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1));

  SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));

    -------------------------------------------------------------------
    -- Wire Delays
    -------------------------------------------------------------------
    WireDelay: BLOCK
    BEGIN

        w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_20 : VitalWireDelay (ENWNeg_ipd, ENWNeg, tipd_ENWNeg);
        w_21 : VitalWireDelay (ENRNeg_ipd, ENRNeg, tipd_ENRNeg);
        w_22 : VitalWireDelay (CKW_ipd, CKW, tipd_CKW);
        w_23 : VitalWireDelay (CKR_ipd, CKR, tipd_CKR);
        w_24 : VitalWireDelay (XINeg_ipd, XINeg, tipd_XINeg);
        w_25 : VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg);
        w_26 : VitalWireDelay (MRNeg_ipd, MRNeg, tipd_MRNeg);
        w_27 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);

    END BLOCK WireDelay;

    D0_nwv      <= To_UX01 (s => D0_ipd);
    D1_nwv      <= To_UX01 (s => D1_ipd);
    D2_nwv      <= To_UX01 (s => D2_ipd);
    D3_nwv      <= To_UX01 (s => D3_ipd);
    D4_nwv      <= To_UX01 (s => D4_ipd);
    D5_nwv      <= To_UX01 (s => D5_ipd);
    D6_nwv      <= To_UX01 (s => D6_ipd);
    D7_nwv      <= To_UX01 (s => D7_ipd);
    D8_nwv      <= To_UX01 (s => D8_ipd);
    ENWNeg_nwv  <= To_UX01 (s => ENWNeg_ipd);
    ENRNeg_nwv  <= To_UX01 (s => ENRNeg_ipd);
    CKW_nwv     <= To_UX01 (s => CKW_ipd);
    CKR_nwv     <= To_UX01 (s => CKR_ipd);
    MRNeg_nwv   <= To_UX01 (s => MRNeg_ipd);
    OENeg_nwv   <= To_UX01 (s => OENeg_ipd);
    XINeg_nwv   <= To_UX01 (s => XINeg_ipd);
    FLNeg_nwv   <= To_UX01 (s => FLNeg_ipd);
    
    -------------------------------------------------------------------
    --  Main behavior Block
    -------------------------------------------------------------------

    VitalBehavior: BLOCK

        PORT (
            Data    : IN    STD_LOGIC_VECTOR(FIFOWordLenght-1 downto 0);
            Q       : OUT   STD_LOGIC_VECTOR(FIFOWordLenght-1 downto 0);
            ENWNeg  : IN    std_Ulogic := 'U';
            ENRNeg  : IN    std_Ulogic := 'U';
            CKW     : IN    std_Ulogic := 'U';
            CKR     : IN    std_Ulogic := 'U';
            HFNeg   : OUT   std_Ulogic := 'U';
            ENeg    : OUT   std_Ulogic := 'U';
            XONeg   : OUT   std_Ulogic := 'U';
            XINeg   : IN    std_Ulogic := 'U';
            FLNeg   : IN    std_Ulogic := 'U';
            MRNeg   : IN    std_Ulogic := 'U';
            OENeg   : IN    std_Ulogic := 'U'
              );

        PORT MAP (
            Data(0) => D0_nwv,
            Data(1) => D1_nwv,
            Data(2) => D2_nwv,
            Data(3) => D3_nwv,
            Data(4) => D4_nwv,
            Data(5) => D5_nwv,
            Data(6) => D6_nwv,
            Data(7) => D7_nwv,
            Data(8) => D8_nwv,
            Q(0)    => Q0,
            Q(1)    => Q1,
            Q(2)    => Q2,
            Q(3)    => Q3,
            Q(4)    => Q4,
            Q(5)    => Q5,
            Q(6)    => Q6,
            Q(7)    => Q7,
            Q(8)    => Q8,
            ENWNeg  => ENWNeg_nwv,
            ENRNeg  => ENRNeg_nwv,
            CKW     => CKW_nwv,
            CKR     => CKR_nwv,
            XINeg   => XINeg_nwv,
            FLNeg   => FLNeg_nwv,
            MRNeg   => MRNeg_nwv,
            OENeg   => OENeg_nwv,
            HFNeg   => HFNeg,
            ENeg    => ENeg,
            XONeg   => XONeg
        );

    SIGNAL ENeg_zd       : STD_ULOGIC := 'X';      ---------------------
    SIGNAL HFNeg_zd      : STD_ULOGIC := 'X';      -- regs for output --
    SIGNAL XONeg_zd      : STD_ULOGIC := 'X';      -- flags           --
    SIGNAL Q_zd          : STD_LOGIC_VECTOR(FIFOWordLenght-1 DOWNTO 0)
                         :=(OTHERS=>'X');

    BEGIN  -- VitalBehavior block

    ---------------------------------------------------------------
    -- Timinf Check Section
    ---------------------------------------------------------------

        MainReadWrite:PROCESS (Data,ENWNeg, ENRNeg, CKW, CKR, 
                               FLNeg, MRNeg, XINeg, OENeg)


            VARIABLE FIFOMemory : FIFOArray;
            TYPE fifo_mode_type IS (unk, single, first_exp, other_exp);
            TYPE stat_type IS (inact, act);

            VARIABLE check_parity : STD_LOGIC:='X';
            VARIABLE fifo_mode  : fifo_mode_type:=unk;
            VARIABLE rd_stat    : stat_type;