fifo7881.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
--  File Name: fifo7881.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998, 2000 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    98 JUN 11   initial release
--    V1.1    R. Munden    00 SEP 09   deleted unused signal
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library:    FIFO
--  Technology: TTL
--  Part:       ACT7881
--
--  Desciption: 1K x 18 FIFO
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY fifo7881 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D0         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D9         : VitalDelayType01 := VitalZeroDelay01;
        tipd_D10        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D11        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D12        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D13        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D14        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D15        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D16        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D17        : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSNeg      : VitalDelayType01 := VitalZeroDelay01;
        tipd_WCLK       : VitalDelayType01 := VitalZeroDelay01;
        tipd_WEN1       : VitalDelayType01 := VitalZeroDelay01;
        tipd_WEN2       : VitalDelayType01 := VitalZeroDelay01;
        tipd_RCLK       : VitalDelayType01 := VitalZeroDelay01;
        tipd_REN1       : VitalDelayType01 := VitalZeroDelay01;
        tipd_REN2       : VitalDelayType01 := VitalZeroDelay01;
        tipd_OE         : VitalDelayType01 := VitalZeroDelay01;
        tipd_DAFNeg     : VitalDelayType01 := VitalZeroDelay01;

        -- tpd delays: propagation delays
        tpd_RSNeg_AF            : VitalDelayType01:= UnitDelay01;
        tpd_RSNeg_HF            : VitalDelayType01:= UnitDelay01;
        tpd_RSNeg_Q0            : VitalDelayType01Z:= UnitDelay01Z;
        tpd_RCLK_Q0             : VitalDelayType01Z:= UnitDelay01Z;
        tpd_OE_Q0               : VitalDelayType01Z:= UnitDelay01Z;
        tpd_WCLK_IRF            : VitalDelayType01 := UnitDelay01;
        tpd_RCLK_ORF            : VitalDelayType01 := UnitDelay01;
        tpd_RCLK_AF             : VitalDelayType01 := UnitDelay01;
        tpd_RCLK_HF             : VitalDelayType01 := UnitDelay01;

        -- tpw values: pulse widths
        tpw_RCLK_posedge        : VitalDelayType := UnitDelay;
        tpw_RCLK_negedge        : VitalDelayType := UnitDelay;
        tpw_WCLK_posedge        : VitalDelayType := UnitDelay;
        tpw_WCLK_negedge        : VitalDelayType := UnitDelay;
        tpw_RSNeg_negedge       : VitalDelayType := UnitDelay;
        tpw_DAFNeg_posedge      : VitalDelayType := UnitDelay;

        -- tperiod min (calculated as 1/max freq)
        tperiod_RCLK_posedge    : VitalDelayType := UnitDelay;

        -- tsetup values: setup times
        tsetup_D0_WCLK          : VitalDelayType := UnitDelay;
        tsetup_D0_DAFNeg        : VitalDelayType := UnitDelay;
        tsetup_WEN1_WCLK        : VitalDelayType := UnitDelay;
        tsetup_REN1_RCLK        : VitalDelayType := UnitDelay;
        tsetup_OE_RCLK          : VitalDelayType := UnitDelay;
        tsetup_RSNeg_RCLK       : VitalDelayType := UnitDelay;
        tsetup_DAFNeg_RSNeg     : VitalDelayType := UnitDelay;

        -- thold values: hold times
        thold_D0_WCLK           : VitalDelayType := UnitDelay;
        thold_D0_DAFNeg         : VitalDelayType := UnitDelay;
        thold_WEN1_WCLK         : VitalDelayType := UnitDelay;
        thold_REN1_RCLK         : VitalDelayType := UnitDelay;
        thold_OE_RCLK           : VitalDelayType := UnitDelay;
        thold_RSNeg_RCLK        : VitalDelayType := UnitDelay;
        thold_DAFNeg_RSNeg      : VitalDelayType := UnitDelay;

        -- generic control parameters
        InstancePath   : STRING  := DefaultInstancePath;
        TimingChecksOn : BOOLEAN := DefaultTimingChecks;
        MsgOn          : BOOLEAN := DefaultMsgOn;
        XOn            : BOOLEAN := DefaultXOn;
        TimingModel    : STRING  := DefaultTimingModel
    );

    PORT (
        D0      : IN    std_logic := 'X';  -- Data Input Bus
        D1      : IN    std_logic := 'X';
        D2      : IN    std_logic := 'X';
        D3      : IN    std_logic := 'X';
        D4      : IN    std_logic := 'X';
        D5      : IN    std_logic := 'X';
        D6      : IN    std_logic := 'X';
        D7      : IN    std_logic := 'X';
        D8      : IN    std_logic := 'X';
        D9      : IN    std_logic := 'X';
        D10     : IN    std_logic := 'X';
        D11     : IN    std_logic := 'X';
        D12     : IN    std_logic := 'X';
        D13     : IN    std_logic := 'X';
        D14     : IN    std_logic := 'X';
        D15     : IN    std_logic := 'X';
        D16     : IN    std_logic := 'X';
        D17     : IN    std_logic := 'X';

        RSNeg   : IN    std_logic := 'X';  -- Reset

        WCLK    : IN    std_logic := 'X';  -- Write Clock
        WEN1    : IN    std_logic := 'X';  -- Write Enable
        WEN2    : IN    std_logic := 'X';  -- Write Enable
        RCLK    : IN    std_logic := 'X';  -- Read Clock
        REN1    : IN    std_logic := 'X';  -- Read Enable
        REN2    : IN    std_logic := 'X';  -- Read Enable

        OE      : IN    std_logic := 'X';  -- Output Enable
        DAFNeg  : IN    std_logic := 'X';  -- Write Expansion Input

        AF      : OUT   std_logic := 'U';  -- Programmable Almost Full/Empty Flag
        HF      : OUT   std_logic := 'U';  -- Half-Full Flag
        IRF     : OUT   std_logic := 'U';  -- Input Ready Flag
        ORF     : OUT   std_logic := 'U';  -- Output Ready Flag

        Q0      : OUT   std_logic := 'U';  -- Data Output Bus
        Q1      : OUT   std_logic := 'U';
        Q2      : OUT   std_logic := 'U';
        Q3      : OUT   std_logic := 'U';
        Q4      : OUT   std_logic := 'U';
        Q5      : OUT   std_logic := 'U';
        Q6      : OUT   std_logic := 'U';
        Q7      : OUT   std_logic := 'U';
        Q8      : OUT   std_logic := 'U';
        Q9      : OUT   std_logic := 'U';
        Q10     : OUT   std_logic := 'U';
        Q11     : OUT   std_logic := 'U';
        Q12     : OUT   std_logic := 'U';
        Q13     : OUT   std_logic := 'U';
        Q14     : OUT   std_logic := 'U';
        Q15     : OUT   std_logic := 'U';
        Q16     : OUT   std_logic := 'U';
        Q17     : OUT   std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 OF fifo7881 : ENTITY IS TRUE;

END fifo7881;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF fifo7881 IS
    ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;

    TYPE statetype IS ARRAY (0 to 3) OF std_ulogic ;
    TYPE mem_type IS ARRAY (0 to 1023 ) OF std_ulogic_vector(17 downto 0) ;

    SIGNAL wordcount : INTEGER := 0 ;

    SIGNAL D0_ipd              : std_ulogic := 'X';
    SIGNAL D1_ipd              : std_ulogic := 'X';
    SIGNAL D2_ipd              : std_ulogic := 'X';
    SIGNAL D3_ipd              : std_ulogic := 'X';
    SIGNAL D4_ipd              : std_ulogic := 'X';
    SIGNAL D5_ipd              : std_ulogic := 'X';
    SIGNAL D6_ipd              : std_ulogic := 'X';
    SIGNAL D7_ipd              : std_ulogic := 'X';
    SIGNAL D8_ipd              : std_ulogic := 'X';
    SIGNAL D9_ipd              : std_ulogic := 'X';
    SIGNAL D10_ipd             : std_ulogic := 'X';
    SIGNAL D11_ipd             : std_ulogic := 'X';
    SIGNAL D12_ipd             : std_ulogic := 'X';
    SIGNAL D13_ipd             : std_ulogic := 'X';
    SIGNAL D14_ipd             : std_ulogic := 'X';
    SIGNAL D15_ipd             : std_ulogic := 'X';
    SIGNAL D16_ipd             : std_ulogic := 'X';
    SIGNAL D17_ipd             : std_ulogic := 'X';
    SIGNAL RSNeg_ipd           : std_ulogic := 'X';
    SIGNAL WCLK_ipd            : std_ulogic := 'X';
    SIGNAL WEN1_ipd            : std_ulogic := 'X';
    SIGNAL WEN2_ipd            : std_ulogic := 'X';
    SIGNAL RCLK_ipd            : std_ulogic := 'X';
    SIGNAL REN1_ipd            : std_ulogic := 'X';
    SIGNAL REN2_ipd            : std_ulogic := 'X';
    SIGNAL OE_ipd              : std_ulogic := 'X';
    SIGNAL DAFNeg_ipd          : std_ulogic := 'X';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_2: VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_3: VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_4: VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_5: VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_6: VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_7: VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_8: VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_9: VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_10: VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_11: VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_12: VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_13: VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_14: VitalWireDelay (D13_ipd, D13, tipd_D13);
        w_15: VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_16: VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_17: VitalWireDelay (D16_ipd, D16, tipd_D16);
        w_18: VitalWireDelay (D17_ipd, D17, tipd_D17);
        w_19: VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);
        w_20: VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        w_21: VitalWireDelay (WEN1_ipd, WEN1, tipd_WEN1);
        w_22: VitalWireDelay (WEN2_ipd, WEN2, tipd_WEN2);
        w_23: VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);
        w_24: VitalWireDelay (REN1_ipd, REN1, tipd_REN1);
        w_25: VitalWireDelay (REN2_ipd, REN2, tipd_REN2);
        w_26: VitalWireDelay (OE_ipd, OE, tipd_OE);
        w_27: VitalWireDelay (DAFNeg_ipd, DAFNeg, tipd_DAFNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- VITALBehavior Process
    ----------------------------------------------------------------------------
        VITALBehavior1 : PROCESS(RSNeg_ipd, WCLK_ipd, RCLK_ipd, OE_ipd, REN1_ipd,
                                 REN2_ipd, WEN1_ipd, WEN2_ipd, DAFNeg_ipd)

        VARIABLE flagstate   : statetype := "0000" ;
        VARIABLE wordcounter : INTEGER := 0 ;
        VARIABLE ae_offset   : NATURAL := 0 ;
        VARIABLE af_offset   : NATURAL := 0 ;
        VARIABLE d           : std_logic_vector(17 downto 0) ;
        VARIABLE d_temp      : std_logic_vector(17 downto 0) ;
        VARIABLE wrtclkcount : INTEGER := 0 ;
        VARIABLE rdclkcount  : INTEGER := 0 ;
        VARIABLE i           : INTEGER := 17 ;
        VARIABLE rst         : INTEGER := 2 ;
        VARIABLE memory      : mem_type ;
        VARIABLE waddr       : INTEGER := 0 ;
        VARIABLE raddr       : INTEGER := 0 ;
        VARIABLE irflag      : INTEGER := 2 ;
        VARIABLE orflag      : INTEGER := 2 ;
        VARIABLE hf_limit    : INTEGER := 0 ;
        VARIABLE f_limit     : INTEGER := 0 ;
        VARIABLE ae_limit    : INTEGER := 0 ;
        VARIABLE af_limit    : INTEGER := 0 ;

        -- Timing Check Variables
        VARIABLE Tviol_D0_WCLK  : X01 := '0';
        VARIABLE TD_D0_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D1_WCLK  : X01 := '0';
        VARIABLE TD_D1_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D2_WCLK  : X01 := '0';
        VARIABLE TD_D2_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D3_WCLK  : X01 := '0';
        VARIABLE TD_D3_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D4_WCLK  : X01 := '0';
        VARIABLE TD_D4_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D5_WCLK  : X01 := '0';
        VARIABLE TD_D5_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D6_WCLK  : X01 := '0';
        VARIABLE TD_D6_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D7_WCLK  : X01 := '0';
        VARIABLE TD_D7_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D8_WCLK  : X01 := '0';
        VARIABLE TD_D8_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D9_WCLK  : X01 := '0';
        VARIABLE TD_D9_WCLK     : VitalTimingDataType;

        VARIABLE Tviol_D10_WCLK : X01 := '0';
        VARIABLE TD_D10_WCLK    : VitalTimingDataType;

        VARIABLE Tviol_D11_WCLK : X01 := '0';
        VARIABLE TD_D11_WCLK    : VitalTimingDataType;

        VARIABLE Tviol_D12_WCLK : X01 := '0';
        VARIABLE TD_D12_WCLK    : VitalTimingDataType;

        VARIABLE Tviol_D13_WCLK : X01 := '0';
        VARIABLE TD_D13_WCLK    : VitalTimingDataType;

        VARIABLE Tviol_D14_WCLK : X01 := '0';
        VARIABLE TD_D14_WCLK    : VitalTimingDataType;