idt723616.vhd

VHDL的ram和fifo model code 包含众多的厂家

    C(4)   	=> C4_ipd,
    C(5)   	=> C5_ipd,
    C(6)   	=> C6_ipd,
    C(7)   	=> C7_ipd,
    C(8)   	=> C8_ipd,
    C(9)   	=> C9_ipd,
    C(10)  	=> C10_ipd,
    C(11)  	=> C11_ipd,
    C(12)  	=> C12_ipd,
    C(13)  	=> C13_ipd,
    C(14)  	=> C14_ipd,
    C(15)  	=> C15_ipd,
    C(16)  	=> C16_ipd,
    C(17)  	=> C17_ipd,
    CLKA        => CLKA_ipd,
    CLKB        => CLKB_ipd,
    CLKC        => CLKC_ipd,
    CSANeg      => CSANeg_ipd,
    EFANeg   	=> EFANeg,
    EFBNeg   	=> EFBNeg,
    ENA         => ENA_ipd,
    FFANeg   	=> FFANeg,
    FFCNeg   	=> FFCNeg,
    FS0         => FS0_ipd,
    FS1         => FS1_ipd,
    ODDEVEN     => ODDEVEN_ipd,
    PEFANeg  	=> PEFANeg,
    PEFCNeg  	=> PEFCNeg,
    PGA         => PGA_ipd,
    PGB         => PGB_ipd,
    RENB        => RENB_ipd,
    RSTNeg      => RSTNeg_ipd,
    SIZ0        => SIZ0_ipd,
    SIZ1        => SIZ1_ipd,
    SWB0        => SWB0_ipd,
    SWB1        => SWB1_ipd,
    SWC0        => SWC0_ipd,
    SWC1        => SWC1_ipd,
    WRA         => WRA_ipd,
    WENC        => WENC_ipd);
    
  -- zero delayed outputs and bidirectional ports 
  -- (func. sec. uses these signals instead of =
  --  actual outputs and bidirectional ports);
  -- actual outputs are assigned in Path Delay Section
  
  SIGNAL A_zd         : std_logic_vector (35 downto 0);
  SIGNAL B_zd         : std_logic_vector (17 downto 0); 
  SIGNAL AEANeg_zd    : std_logic; 
  SIGNAL AEBNeg_zd    : std_logic;  
  SIGNAL AFANeg_zd    : std_logic;  
  SIGNAL AFCNeg_zd    : std_logic;  
  SIGNAL EFANeg_zd    : std_logic;     
  SIGNAL EFBNeg_zd    : std_logic;     
  SIGNAL FFANeg_zd    : std_logic;     
  SIGNAL FFCNeg_zd    : std_logic;     
  SIGNAL PEFANeg_zd   : std_logic;    
  SIGNAL PEFCNeg_zd   : std_logic;   

  ------------------------------------------------------------------------------
  -- FIFO memory definitions
  ------------------------------------------------------------------------------
  -- general
  CONSTANT FIFOSize        :  positive := 64;
  CONSTANT FIFOWordLength  :  positive := 36;
  SUBTYPE  FIFOWord    IS std_logic_vector(FIFOWordLength - 1 DOWNTO 0);
  TYPE     FIFOArray   IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord;
  
  -- special
  CONSTANT FIFOWordBytes   :  positive := 4;
  
  ------------------------------------------------------------------------------
  -- internal constants 
  ------------------------------------------------------------------------------
  
     CONSTANT SIZByte : std_logic_vector (1 DOWNTO 0) := "10";	
     CONSTANT SIZWord : std_logic_vector (1 DOWNTO 0) := "01";    
  
  ------------------------------------------------------------------------------
  -- internal signals 
  ------------------------------------------------------------------------------
  
  -- FIFO Arrays
  
     SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
     SIGNAL FIFOMemory2int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
                                        
  -- Main Registers                                       
  
     -- Input Registers
      
     SIGNAL InputReg1int   : FIFOWord := (OTHERS => 'X');
     SIGNAL InputReg2int   : FIFOWord := (OTHERS => 'X'); 
     
     -- Output Registers
      
     SIGNAL OutputReg1int  : FIFOWord := (OTHERS => 'X');
     SIGNAL OutputReg2int  : FIFOWord := (OTHERS => 'X');
     
     -- FIFO Pointers
     
     SIGNAL ReadPtr1int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL ReadPtr2int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr1int   : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr2int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- FIFO Offset for Almoust Empty/Full Flags
     
     SIGNAL EmptyOffsRegint: Natural RANGE 0 TO FIFOSize-1;
     SIGNAL FullOffsRegint : Natural RANGE 0 TO FIFOSize-1;

     -- Flags Flip-flop first stage (each flag is synchonized 
     -- to its Port Clock through two flip-flop stages)
     
     SIGNAL EFA1int, EFB1int, FFA1int, FFC1int, 
            AEA1int, AEB1int, AFA1int, AFC1int : std_logic;
            
    -- Flags "Input Register is loaded" - in this 
     -- model they will be loaded to FIFOMemory on CLK negedge      
      
     SIGNAL InputReg1Readyint   : std_logic; 
     SIGNAL InputReg2Readyint   : std_logic; 
     SIGNAL InputReg2ReadyNextint   : std_logic; 
     
     -- Pointers for Byte/Word Access for PortB/PortC
        
     SIGNAL OutputReg1Ptrint : Natural RANGE 0 TO FIFOWordBytes-1;
     SIGNAL InputReg2Ptrint  : Natural RANGE 0 TO FIFOWordBytes-1;
     
     SIGNAL OutputReg1Readyint : std_logic; -- all 4-bytes have been
     				 	    -- read to Port-B 
     SIGNAL OutputReg1ReadyNextint : std_logic;
                                            -- all 4-bytes will be 
     				 	    -- read to Port-B next CLKB
     				 	    -- posedge
	     						   
       -- Pointers for Byte/Word Access that will be latched on CLKB posedge
       	     						   
       SIGNAL OutputReg1PtrNextint   : Natural RANGE 0 TO FIFOWordBytes - 1;
       
     -- Registers for control ports 
  
     SIGNAL SWBint      : std_logic_vector (1 downto 0);  -- (SWB1, SWB0) 		
     SIGNAL SWCint      : std_logic_vector (1 downto 0);  -- (SWC1, SWC0) 		
     SIGNAL SIZBint     : std_logic_vector (1 downto 0);  -- (SIZ1, SIZ0) 
                                                          -- on CLKB posedge 	
     SIGNAL SIZCint     : std_logic_vector (1 downto 0);  -- (SIZ1, SIZ0) 
                                                          -- on CLKC posedge 	
  
     SIGNAL SIZCprevint : std_logic_vector (1 downto 0);  -- (SIZ1, SIZ0) 
 	-- on previous CLKC posedge
  
     -- Counters of Clocks during RSTNeg is active or passive
     
     SIGNAL CountCLKAint, CountCLKBint, CountCLKCint: Natural;
  
    -------------------------------------------------------------------    
    -- Swap Bytes/Words in 36-bit word
    -------------------------------------------------------------------    
    FUNCTION FIFOSwap
      	(Data      : in std_logic_vector (35 downto 0);	-- Data
         SwapCode  : in std_logic_vector (1 downto 0))
       -- SwapCode = "00" - NO SWAP 	
       -- SwapCode = "01" - BYTE SWAP 	
       -- SwapCode = "10" - WORD SWAP 	
       -- SwapCode = "11" - BYTE-WORD SWAP	
         RETURN  std_logic_vector --(35 downto 0)
    IS  
        VARIABLE Result: std_logic_vector (35 downto 0);
    BEGIN
	CASE SwapCode IS
	    WHEN "00" => 
	      Result := Data;
	    WHEN "01" =>
	      Result(8 DOWNTO 0)  := Data(35 DOWNTO 27);
	      Result(17 DOWNTO 9) := Data(26 DOWNTO 18);
	      Result(26 DOWNTO 18):= Data(17 DOWNTO 9);
	      Result(35 DOWNTO 27):= Data(8 DOWNTO 0);
	    WHEN "10" =>
	      Result(17 DOWNTO 0) := Data(35 DOWNTO 18);
	      Result(35 DOWNTO 18):= Data(17 DOWNTO 0);
	    WHEN "11" =>
	      Result(8 DOWNTO 0)  := Data(17 DOWNTO 9);
	      Result(17 DOWNTO 9) := Data(8 DOWNTO 0);
	      Result(26 DOWNTO 18):= Data(35 DOWNTO 27);
	      Result(35 DOWNTO 27):= Data(26 DOWNTO 18);
	    WHEN OTHERS => 
	      Result := (OTHERS => 'X');  
	END CASE;             
    	RETURN Result;
    END FIFOSwap;
    
  BEGIN -- VitalBehavior block
     
--------------------------------------------------------------------------------
-- Timing Check Section                                                         --
--------------------------------------------------------------------------------

     TimingChecks: PROCESS ( A_ipd, C, CLKA, CLKB, CLKC, CSANeg, ENA,
       FS0, FS1, ODDEVEN, PGA, PGB, RENB, RSTNeg, SIZ0, SIZ1, SWB0, SWB1,
       SWC0, SWC1, WRA, WENC)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKC          : X01 := '0';
      VARIABLE PD_CLKC             : VitalPeriodDataType := VitalPeriodDataInit;
    
    -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_C0_CLKC       : X01 := '0';
      VARIABLE TD_C0_CLKC          : VitalTimingDataType;

      VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENA_CLKA      : X01 := '0';
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_RENB_CLKB     : X01 := '0';
      VARIABLE TD_RENB_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_WENC_CLKC     : X01 := '0';
      VARIABLE TD_WENC_CLKC        : VitalTimingDataType;
    
      VARIABLE Tviol_SIZ0_CLKB     : X01 := '0';
      VARIABLE TD_SIZ0_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_SIZ1_CLKB     : X01 := '0';
      VARIABLE TD_SIZ1_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_SIZ0_CLKC     : X01 := '0';
      VARIABLE TD_SIZ0_CLKC        : VitalTimingDataType;

      VARIABLE Tviol_SIZ1_CLKC     : X01 := '0';
      VARIABLE TD_SIZ1_CLKC        : VitalTimingDataType;

      VARIABLE Tviol_SWB0_CLKB     : X01 := '0';
      VARIABLE TD_SWB0_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_SWB1_CLKB     : X01 := '0';
      VARIABLE TD_SWB1_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_SWC0_CLKC     : X01 := '0';
      VARIABLE TD_SWC0_CLKC        : VitalTimingDataType;

      VARIABLE Tviol_SWC1_CLKC     : X01 := '0';
      VARIABLE TD_SWC1_CLKC        : VitalTimingDataType;

      VARIABLE Tviol_ODDEVEN_CLKA  : X01 := '0';
      VARIABLE TD_ODDEVEN_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PGA_CLKA      : X01 := '0';
      VARIABLE TD_PGA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ODDEVEN_CLKB  : X01 := '0';
      VARIABLE TD_ODDEVEN_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_PGB_CLKB      : X01 := '0';
      VARIABLE TD_PGB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_RSTNeg_CLKA   : X01 := '0';
      VARIABLE TD_RSTNeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_RSTNeg_CLKB   : X01 := '0';
      VARIABLE TD_RSTNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_RSTNeg_CLKC   : X01 := '0';
      VARIABLE TD_RSTNeg_CLKC      : VitalTimingDataType;

      VARIABLE Tviol_FS0_RSTNeg    : X01 := '0';
      VARIABLE TD_FS0_RSTNeg       : VitalTimingDataType;

      VARIABLE Tviol_FS1_RSTNeg    : X01 := '0';
      VARIABLE TD_FS1_RSTNeg       : VitalTimingDataType;

    -- Violation variable (used to OR all individual violation variables)

      VARIABLE Violation           : X01 := '0';
    
BEGIN

--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------
 IF  (TimingChecksOn)
 THEN

      -- CLKA period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKA,
          TestSignalName  => "CLKA",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKA);

      -- CLKB period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKB,
          TestSignalName  => "CLKB",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKB);

      -- CLKC period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKC,
          TestSignalName  => "CLKC",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,