idt723616.vhd

VHDL的ram和fifo model code 包含众多的厂家

    -- (func. sec. must use these signals instead of actual inputs/inoutputs)

  SIGNAL A0_ipd       : std_ulogic := 'X';
  SIGNAL A1_ipd       : std_ulogic := 'X';
  SIGNAL A2_ipd       : std_ulogic := 'X';
  SIGNAL A3_ipd       : std_ulogic := 'X';
  SIGNAL A4_ipd       : std_ulogic := 'X';
  SIGNAL A5_ipd       : std_ulogic := 'X';
  SIGNAL A6_ipd       : std_ulogic := 'X';
  SIGNAL A7_ipd       : std_ulogic := 'X';
  SIGNAL A8_ipd       : std_ulogic := 'X';
  SIGNAL A9_ipd       : std_ulogic := 'X';
  SIGNAL A10_ipd      : std_ulogic := 'X';
  SIGNAL A11_ipd      : std_ulogic := 'X';
  SIGNAL A12_ipd      : std_ulogic := 'X';
  SIGNAL A13_ipd      : std_ulogic := 'X';
  SIGNAL A14_ipd      : std_ulogic := 'X';
  SIGNAL A15_ipd      : std_ulogic := 'X';
  SIGNAL A16_ipd      : std_ulogic := 'X';
  SIGNAL A17_ipd      : std_ulogic := 'X';
  SIGNAL A18_ipd      : std_ulogic := 'X';
  SIGNAL A19_ipd      : std_ulogic := 'X';
  SIGNAL A20_ipd      : std_ulogic := 'X';
  SIGNAL A21_ipd      : std_ulogic := 'X';
  SIGNAL A22_ipd      : std_ulogic := 'X';
  SIGNAL A23_ipd      : std_ulogic := 'X';
  SIGNAL A24_ipd      : std_ulogic := 'X';
  SIGNAL A25_ipd      : std_ulogic := 'X';
  SIGNAL A26_ipd      : std_ulogic := 'X';
  SIGNAL A27_ipd      : std_ulogic := 'X';
  SIGNAL A28_ipd      : std_ulogic := 'X';
  SIGNAL A29_ipd      : std_ulogic := 'X';
  SIGNAL A30_ipd      : std_ulogic := 'X';
  SIGNAL A31_ipd      : std_ulogic := 'X';
  SIGNAL A32_ipd      : std_ulogic := 'X';
  SIGNAL A33_ipd      : std_ulogic := 'X';
  SIGNAL A34_ipd      : std_ulogic := 'X';
  SIGNAL A35_ipd      : std_ulogic := 'X';
  SIGNAL C0_ipd       : std_ulogic := 'X';
  SIGNAL C1_ipd       : std_ulogic := 'X';
  SIGNAL C2_ipd       : std_ulogic := 'X';
  SIGNAL C3_ipd       : std_ulogic := 'X';
  SIGNAL C4_ipd       : std_ulogic := 'X';
  SIGNAL C5_ipd       : std_ulogic := 'X';
  SIGNAL C6_ipd       : std_ulogic := 'X';
  SIGNAL C7_ipd       : std_ulogic := 'X';
  SIGNAL C8_ipd       : std_ulogic := 'X';
  SIGNAL C9_ipd       : std_ulogic := 'X';
  SIGNAL C10_ipd      : std_ulogic := 'X';
  SIGNAL C11_ipd      : std_ulogic := 'X';
  SIGNAL C12_ipd      : std_ulogic := 'X';
  SIGNAL C13_ipd      : std_ulogic := 'X';
  SIGNAL C14_ipd      : std_ulogic := 'X';
  SIGNAL C15_ipd      : std_ulogic := 'X';
  SIGNAL C16_ipd      : std_ulogic := 'X';
  SIGNAL C17_ipd      : std_ulogic := 'X';
  SIGNAL CLKA_ipd     : std_ulogic := 'X';
  SIGNAL CLKB_ipd     : std_ulogic := 'X';
  SIGNAL CLKC_ipd     : std_ulogic := 'X';
  SIGNAL CSANeg_ipd   : std_ulogic := 'X';
  SIGNAL ENA_ipd      : std_ulogic := 'X';
  SIGNAL FS0_ipd      : std_ulogic := 'X';
  SIGNAL FS1_ipd      : std_ulogic := 'X';
  SIGNAL ODDEVEN_ipd  : std_ulogic := 'X';
  SIGNAL PGA_ipd      : std_ulogic := 'X';
  SIGNAL PGB_ipd      : std_ulogic := 'X';
  SIGNAL RENB_ipd     : std_ulogic := 'X';
  SIGNAL RSTNeg_ipd   : std_ulogic := 'X';
  SIGNAL SIZ0_ipd     : std_ulogic := 'X';
  SIGNAL SIZ1_ipd     : std_ulogic := 'X';
  SIGNAL SWB0_ipd     : std_ulogic := 'X';
  SIGNAL SWB1_ipd     : std_ulogic := 'X';
  SIGNAL SWC0_ipd     : std_ulogic := 'X';
  SIGNAL SWC1_ipd     : std_ulogic := 'X';
  SIGNAL WRA_ipd      : std_ulogic := 'X';
  SIGNAL WENC_ipd     : std_ulogic := 'X';  
  
  SIGNAL OpenIn, OpenOut : std_logic; -- Additional signals
  
  ALIAS   tA	: VitalDelayType01 	IS tpd_CLKA_A0;
  ALIAS   tWFF	: VitalDelayType01	IS tpd_CLKA_FFANeg;
  ALIAS   tREF	: VitalDelayType01	IS tpd_CLKA_EFANeg;
  ALIAS   tPAE	: VitalDelayType01	IS tpd_CLKA_AEANeg;
  ALIAS   tPAF	: VitalDelayType01	IS tpd_CLKA_AFANeg;
  ALIAS   tPPE	: VitalDelayType01	IS tpd_CLKC_PEFCNeg;
  ALIAS   tPDPE	: VitalDelayType01	IS tpd_A0_PEFANEg;
  ALIAS   tPOPE	: VitalDelayType01	IS tpd_ODDEVEN_PEFANeg;
  ALIAS   tPEPE	: VitalDelayType01	IS tpd_PGA_PEFANeg;
  ALIAS   tEN_DIS: VitalDelayType01Z	IS tpd_CSANeg_A0;
  ALIAS   tCLK	: VitalDelayType	IS tperiod_CLKA_posedge;
  ALIAS   tCLKH	: VitalDelayType	IS tpw_CLKA_posedge;
  ALIAS   tCLKL	: VitalDelayType	IS tpw_CLKA_negedge;
  ALIAS   tDS	: VitalDelayType	IS tsetup_A0_CLKA;
  ALIAS   tENS	: VitalDelayType	IS tsetup_CSANeg_CLKA;
  ALIAS   tSZS	: VitalDelayType	IS tsetup_SIZ0_CLKB;
  ALIAS   tSWS	: VitalDelayType	IS tsetup_SWB0_CLKB;
  ALIAS   tPGS	: VitalDelayType	IS tsetup_ODDEVEN_CLKA;
  ALIAS   tRSTS	: VitalDelayType	IS tsetup_RSTNeg_CLKA;
  ALIAS   tFSS	: VitalDelayType	IS tsetup_FS0_RSTNeg;
  ALIAS   tDH	: VitalDelayType	IS thold_A0_CLKA;
  ALIAS   tENH	: VitalDelayType	IS thold_CSANeg_CLKA;
  ALIAS   tSZH	: VitalDelayType	IS thold_SIZ0_CLKB;
  ALIAS   tSWH 	: VitalDelayType	IS thold_SWB0_CLKB;
  ALIAS   tPGH	: VitalDelayType	IS thold_ODDEVEN_CLKA;
  ALIAS   tRSTH	: VitalDelayType	IS thold_RSTNeg_CLKA;
  ALIAS   tFSH	: VitalDelayType	IS thold_FS0_RSTNeg;
     
BEGIN

--------------------------------------------------------------------------------
-- Skew Delays 
--------------------------------------------------------------------------------
-- Artificient VITAL primitives wich allows pass complex non-constaint 
-- SKEW time into the model            
SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1));

SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));

--------------------------------------------------------------------------------
-- Wire Delays                                                                --
--------------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN

    w_1:  VitalWireDelay (A0_ipd,       A0,       tipd_A0      );
    w_2:  VitalWireDelay (A1_ipd,       A1,       tipd_A1      );
    w_3:  VitalWireDelay (A2_ipd,       A2,       tipd_A2      );
    w_4:  VitalWireDelay (A3_ipd,       A3,       tipd_A3      );
    w_5:  VitalWireDelay (A4_ipd,       A4,       tipd_A4      );
    w_6:  VitalWireDelay (A5_ipd,       A5,       tipd_A5      );
    w_7:  VitalWireDelay (A6_ipd,       A6,       tipd_A6      );
    w_8:  VitalWireDelay (A7_ipd,       A7,       tipd_A7      );
    w_9:  VitalWireDelay (A8_ipd,       A8,       tipd_A8      );
    w_10: VitalWireDelay (A9_ipd,       A9,       tipd_A9      );
    w_11: VitalWireDelay (A10_ipd,      A10,      tipd_A10     );
    w_12: VitalWireDelay (A11_ipd,      A11,      tipd_A11     );
    w_13: VitalWireDelay (A12_ipd,      A12,      tipd_A12     );
    w_14: VitalWireDelay (A13_ipd,      A13,      tipd_A13     );
    w_15: VitalWireDelay (A14_ipd,      A14,      tipd_A14     );
    w_16: VitalWireDelay (A15_ipd,      A15,      tipd_A15     );
    w_17: VitalWireDelay (A16_ipd,      A16,      tipd_C16     );
    w_18: VitalWireDelay (A17_ipd,      A17,      tipd_A17     );
    w_19: VitalWireDelay (A18_ipd,      A18,      tipd_A18     );
    w_20: VitalWireDelay (A19_ipd,      A19,      tipd_A19     );
    w_21: VitalWireDelay (A20_ipd,      A20,      tipd_A20     );
    w_22: VitalWireDelay (A21_ipd,      A21,      tipd_A21     );
    w_23: VitalWireDelay (A22_ipd,      A22,      tipd_A22     );
    w_24: VitalWireDelay (A23_ipd,      A23,      tipd_A23     );
    w_25: VitalWireDelay (A24_ipd,      A24,      tipd_A24     );
    w_26: VitalWireDelay (A25_ipd,      A25,      tipd_A25     );
    w_27: VitalWireDelay (A26_ipd,      A26,      tipd_A26     );
    w_28: VitalWireDelay (A27_ipd,      A27,      tipd_A27     );
    w_29: VitalWireDelay (A28_ipd,      A28,      tipd_A28     );
    w_30: VitalWireDelay (A29_ipd,      A29,      tipd_A29     );
    w_31: VitalWireDelay (A30_ipd,      A30,      tipd_A30     );
    w_32: VitalWireDelay (A31_ipd,      A31,      tipd_A31     );
    w_33: VitalWireDelay (A32_ipd,      A32,      tipd_A32     );
    w_34: VitalWireDelay (A33_ipd,      A33,      tipd_A33     );
    w_35: VitalWireDelay (A34_ipd,      A34,      tipd_A34     );
    w_36: VitalWireDelay (A35_ipd,      A35,      tipd_A35     );
    w_37: VitalWireDelay (C0_ipd,       C0,       tipd_C0      );
    w_38: VitalWireDelay (C1_ipd,       C1,       tipd_C1      );
    w_39: VitalWireDelay (C2_ipd,       C2,       tipd_C2      );
    w_40: VitalWireDelay (C3_ipd,       C3,       tipd_C3      );
    w_41: VitalWireDelay (C4_ipd,       C4,       tipd_C4      );
    w_42: VitalWireDelay (C5_ipd,       C5,       tipd_C5      );
    w_43: VitalWireDelay (C6_ipd,       C6,       tipd_C6      );
    w_44: VitalWireDelay (C7_ipd,       C7,       tipd_C7      );
    w_45: VitalWireDelay (C8_ipd,       C8,       tipd_C8      );
    w_46: VitalWireDelay (C9_ipd,       C9,       tipd_C9      );
    w_47: VitalWireDelay (C10_ipd,      C10,      tipd_C10     );
    w_48: VitalWireDelay (C11_ipd,      C11,      tipd_C11     );
    w_49: VitalWireDelay (C12_ipd,      C12,      tipd_C12     );
    w_50: VitalWireDelay (C13_ipd,      C13,      tipd_C13     );
    w_51: VitalWireDelay (C14_ipd,      C14,      tipd_C14     );
    w_52: VitalWireDelay (C15_ipd,      C15,      tipd_C15     );
    w_53: VitalWireDelay (C16_ipd,      C16,      tipd_C16     );
    w_54: VitalWireDelay (C17_ipd,      C17,      tipd_C17     );
    w_55: VitalWireDelay (CLKA_ipd,     CLKA,     tipd_CLKA    );
    w_56: VitalWireDelay (CLKB_ipd,     CLKB,     tipd_CLKB    );
    w_57: VitalWireDelay (CLKC_ipd,     CLKC,     tipd_CLKC    );
    w_58: VitalWireDelay (CSANeg_ipd,   CSANeg,   tipd_CSANeg  );
    w_59: VitalWireDelay (ENA_ipd,      ENA,      tipd_ENA     );
    w_60: VitalWireDelay (FS0_ipd,      FS0,      tipd_FS0     );
    w_61: VitalWireDelay (FS1_ipd,      FS1,      tipd_FS1     );
    w_62: VitalWireDelay (ODDEVEN_ipd,  ODDEVEN,  tipd_ODDEVEN );
    w_63: VitalWireDelay (PGA_ipd,      PGA,      tipd_PGA     );
    w_64: VitalWireDelay (PGB_ipd,      PGB,      tipd_PGB     );
    w_65: VitalWireDelay (RENB_ipd,     RENB,     tipd_RENB    );
    w_66: VitalWireDelay (RSTNeg_ipd,   RSTNeg,   tipd_RSTNeg  );
    w_67: VitalWireDelay (SIZ0_ipd,     SIZ0,     tipd_SIZ0    );
    w_68: VitalWireDelay (SIZ1_ipd,     SIZ1,     tipd_SIZ1    );
    w_69: VitalWireDelay (SWB0_ipd,     SWB0,     tipd_SWB0    );
    w_70: VitalWireDelay (SWB1_ipd,     SWB1,     tipd_SWB1    );
    w_71: VitalWireDelay (SWC0_ipd,     SWC0,     tipd_SWC0    );
    w_72: VitalWireDelay (SWC1_ipd,     SWC1,     tipd_SWC1    );
    w_73: VitalWireDelay (WRA_ipd,      WRA,      tipd_WRA     );
    w_74: VitalWireDelay (WENC_ipd,     WENC,     tipd_WENC    );

END BLOCK;

--------------------------------------------------------------------------------
-- Main Behavior Block                                                        --
--------------------------------------------------------------------------------
  VITALBehavior: BLOCK
  
  PORT (
    A_ipd    : IN std_logic_vector(35 downto 0) := (OTHERS => 'X'); 
    A        : OUT std_logic_vector(35 downto 0) := (OTHERS => 'U'); 
    AEANeg   : OUT   std_logic := 'U'; 
    AEBNeg   : OUT   std_logic := 'U'; 
    AFANeg   : OUT   std_logic := 'U'; 
    AFCNeg   : OUT   std_logic := 'U'; 
    B        : OUT   std_logic_vector(17 downto 0) := (OTHERS => 'U'); 
    C        : IN    std_logic_vector(17 downto 0) := (OTHERS => 'X'); 
    CLKA     : IN    std_logic := 'X'; 
    CLKB     : IN    std_logic := 'X'; 
    CLKC     : IN    std_logic := 'X'; 
    CSANeg   : IN    std_logic := 'X'; 
    EFANeg   : OUT   std_logic := 'U'; 
    EFBNeg   : OUT   std_logic := 'U'; 
    ENA      : IN    std_logic := 'X'; 
    FFANeg   : OUT   std_logic := 'U'; 
    FFCNeg   : OUT   std_logic := 'U'; 
    FS0      : IN    std_logic := 'X'; 
    FS1      : IN    std_logic := 'X'; 
    ODDEVEN  : IN    std_logic := 'X'; 
    PEFANeg  : OUT   std_logic := 'U'; 
    PEFCNeg  : OUT   std_logic := 'U'; 
    PGA      : IN    std_logic := 'X'; 
    PGB      : IN    std_logic := 'X'; 
    RENB     : IN    std_logic := 'X'; 
    RSTNeg   : IN    std_logic := 'X'; 
    SIZ0     : IN    std_logic := 'X'; 
    SIZ1     : IN    std_logic := 'X'; 
    SWB0     : IN    std_logic := 'X'; 
    SWB1     : IN    std_logic := 'X'; 
    SWC0     : IN    std_logic := 'X'; 
    SWC1     : IN    std_logic := 'X'; 
    WRA      : IN    std_logic := 'X'; 
    WENC     : IN    std_logic := 'X'  
     );
   PORT MAP (
    A_ipd(0)    => A0_ipd,
    A_ipd(1)    => A1_ipd,
    A_ipd(2)    => A2_ipd,
    A_ipd(3)    => A3_ipd,
    A_ipd(4)    => A4_ipd,
    A_ipd(5)    => A5_ipd,
    A_ipd(6)    => A6_ipd,
    A_ipd(7)    => A7_ipd,
    A_ipd(8)    => A8_ipd,
    A_ipd(9)    => A9_ipd,
    A_ipd(10)   => A10_ipd,
    A_ipd(11)   => A11_ipd,
    A_ipd(12)   => A12_ipd,
    A_ipd(13)   => A13_ipd,
    A_ipd(14)   => A14_ipd,
    A_ipd(15)   => A15_ipd,
    A_ipd(16)   => A16_ipd,
    A_ipd(17)   => A17_ipd,
    A_ipd(18)   => A18_ipd,
    A_ipd(19)   => A19_ipd,
    A_ipd(20)   => A20_ipd,
    A_ipd(21)   => A21_ipd,
    A_ipd(22)   => A22_ipd,
    A_ipd(23)   => A23_ipd,
    A_ipd(24)   => A24_ipd,
    A_ipd(25)   => A25_ipd,
    A_ipd(26)   => A26_ipd,
    A_ipd(27)   => A27_ipd,
    A_ipd(28)   => A28_ipd,
    A_ipd(29)   => A29_ipd,
    A_ipd(30)   => A30_ipd,
    A_ipd(31)   => A31_ipd,
    A_ipd(32)   => A32_ipd,
    A_ipd(33)   => A33_ipd,
    A_ipd(34)   => A34_ipd,
    A_ipd(35)   => A35_ipd,
    A(0)    	=> A0,
    A(1)    	=> A1,
    A(2)    	=> A2,
    A(3)    	=> A3,
    A(4) 	=> A4,
    A(5)  	=> A5,
    A(6)  	=> A6,
    A(7)    	=> A7,
    A(8)    	=> A8,
    A(9)    	=> A9,
    A(10)   	=> A10,
    A(11)   	=> A11,
    A(12)   	=> A12,
    A(13)   	=> A13,
    A(14)   	=> A14,
    A(15)   	=> A15,
    A(16)   	=> A16,
    A(17)   	=> A17,
    A(18)   	=> A18,
    A(19)   	=> A19,
    A(20)   	=> A20,
    A(21)   	=> A21,
    A(22)   	=> A22,
    A(23)   	=> A23,
    A(24)   	=> A24,
    A(25)   	=> A25,
    A(26)   	=> A26,
    A(27)   	=> A27,
    A(28)   	=> A28,
    A(29)   	=> A29,
    A(30)   	=> A30,
    A(31)   	=> A31,
    A(32)   	=> A32,
    A(33)   	=> A33,
    A(34)   	=> A34,
    A(35)    	=> A35,
    AEANeg  	=> AEANeg,
    AEBNeg   	=> AEBNeg,
    AFANeg   	=> AFANeg,
    AFCNeg   	=> AFCNeg,
    B(0)       	=> B0,
    B(1)       	=> B1,
    B(2)       	=> B2,
    B(3)       	=> B3,
    B(4)       	=> B4,
    B(5)       	=> B5,
    B(6)       	=> B6,
    B(7)       	=> B7,
    B(8)       	=> B8,
    B(9)       	=> B9,
    B(10)      	=> B10,
    B(11)      	=> B11,
    B(12)      	=> B12,
    B(13)      	=> B13,
    B(14)      	=> B14,
    B(15)      	=> B15,
    B(16)      	=> B16,
    B(17)      	=> B17,
    C(0)   	=> C0_ipd, 
    C(1)   	=> C1_ipd,
    C(2)   	=> C2_ipd,
    C(3)   	=> C3_ipd,