📄 idt723616.vhd
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---------------------------------------------------------------------------------- File name : idt723616.vhd--------------------------------------------------------------------------------- Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/-- Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT-- and supported by Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no-- warranty with respect to the information contained herein. IDT DISCLAIMS-- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE-- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN-- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN-- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,-- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR-- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make-- changes without notice to any product herein to improve reliability,-- function, or design. IDT does not convey any license under patent rights-- or any other intellectual property rights, including those of third parties.-- IDT is not obligated to provide maintenance or support for the licensed VHDL-- model.---- MODIFICATION HISTORY :---- version | author | mod date: | changes made-- V1.0 | Anatoli Sokhatski | 98 APR 14 | initial coding-- V1.1 | R. Munden | 02 MAY 19 | licensing changed to GPL----------------------------------------------------------------------------------- PART DESCRIPTION :---- Library: IDT_FIFO-- Technology: CMOS-- Part: IDT723616---- Descripton: Triple Bus SyncFIFO 64x36x2--------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL;LIBRARY fmf; USE fmf.ff_package.ALL; USE fmf.gen_utils.ALL; USE fmf.conversions.to_nat; USE fmf.conversions.to_slv; ---------------------------------------------------------------------------------- ENTITY DECLARATION ----------------------------------------------------------------------------------ENTITY IDT723616 IS GENERIC ( -- tipd delays: interconnect path delays -- (there must be one generic for each input pin) tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_A13 : VitalDelayType01 := VitalZeroDelay01; tipd_A14 : VitalDelayType01 := VitalZeroDelay01; tipd_A15 : VitalDelayType01 := VitalZeroDelay01; tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_A20 : VitalDelayType01 := VitalZeroDelay01; tipd_A21 : VitalDelayType01 := VitalZeroDelay01; tipd_A22 : VitalDelayType01 := VitalZeroDelay01; tipd_A23 : VitalDelayType01 := VitalZeroDelay01; tipd_A24 : VitalDelayType01 := VitalZeroDelay01; tipd_A25 : VitalDelayType01 := VitalZeroDelay01; tipd_A26 : VitalDelayType01 := VitalZeroDelay01; tipd_A27 : VitalDelayType01 := VitalZeroDelay01; tipd_A28 : VitalDelayType01 := VitalZeroDelay01; tipd_A29 : VitalDelayType01 := VitalZeroDelay01; tipd_A30 : VitalDelayType01 := VitalZeroDelay01; tipd_A31 : VitalDelayType01 := VitalZeroDelay01; tipd_A32 : VitalDelayType01 := VitalZeroDelay01; tipd_A33 : VitalDelayType01 := VitalZeroDelay01; tipd_A34 : VitalDelayType01 := VitalZeroDelay01; tipd_A35 : VitalDelayType01 := VitalZeroDelay01; tipd_C0 : VitalDelayType01 := VitalZeroDelay01; tipd_C1 : VitalDelayType01 := VitalZeroDelay01; tipd_C2 : VitalDelayType01 := VitalZeroDelay01; tipd_C3 : VitalDelayType01 := VitalZeroDelay01; tipd_C4 : VitalDelayType01 := VitalZeroDelay01; tipd_C5 : VitalDelayType01 := VitalZeroDelay01; tipd_C6 : VitalDelayType01 := VitalZeroDelay01; tipd_C7 : VitalDelayType01 := VitalZeroDelay01; tipd_C8 : VitalDelayType01 := VitalZeroDelay01; tipd_C9 : VitalDelayType01 := VitalZeroDelay01; tipd_C10 : VitalDelayType01 := VitalZeroDelay01; tipd_C11 : VitalDelayType01 := VitalZeroDelay01; tipd_C12 : VitalDelayType01 := VitalZeroDelay01; tipd_C13 : VitalDelayType01 := VitalZeroDelay01; tipd_C14 : VitalDelayType01 := VitalZeroDelay01; tipd_C15 : VitalDelayType01 := VitalZeroDelay01; tipd_C16 : VitalDelayType01 := VitalZeroDelay01; tipd_C17 : VitalDelayType01 := VitalZeroDelay01; tipd_CLKA : VitalDelayType01 := VitalZeroDelay01; tipd_CLKB : VitalDelayType01 := VitalZeroDelay01; tipd_CLKC : VitalDelayType01 := VitalZeroDelay01; tipd_CSANeg : VitalDelayType01 := VitalZeroDelay01; tipd_ENA : VitalDelayType01 := VitalZeroDelay01; tipd_FS0 : VitalDelayType01 := VitalZeroDelay01; tipd_FS1 : VitalDelayType01 := VitalZeroDelay01; tipd_ODDEVEN : VitalDelayType01 := VitalZeroDelay01; tipd_PGA : VitalDelayType01 := VitalZeroDelay01; tipd_PGB : VitalDelayType01 := VitalZeroDelay01; tipd_RENB : VitalDelayType01 := VitalZeroDelay01; tipd_RSTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SIZ0 : VitalDelayType01 := VitalZeroDelay01; tipd_SIZ1 : VitalDelayType01 := VitalZeroDelay01; tipd_SWB0 : VitalDelayType01 := VitalZeroDelay01; tipd_SWB1 : VitalDelayType01 := VitalZeroDelay01; tipd_SWC0 : VitalDelayType01 := VitalZeroDelay01; tipd_SWC1 : VitalDelayType01 := VitalZeroDelay01; tipd_WRA : VitalDelayType01 := VitalZeroDelay01; tipd_WENC : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays -- tA tpd_CLKA_A0 : VitalDelayType01 := UnitDelay01; -- tWFF tpd_CLKA_FFANeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_CLKA_EFANeg : VitalDelayType01 := UnitDelay01; -- tPAE tpd_CLKA_AEANeg : VitalDelayType01 := UnitDelay01; -- tPAF tpd_CLKA_AFANeg : VitalDelayType01 := UnitDelay01; -- tPPE tpd_CLKC_PEFCNeg : VitalDelayType01 := UnitDelay01; -- tPDPE tpd_A0_PEFANeg : VitalDelayType01 := UnitDelay01; -- tPOPE tpd_ODDEVEN_PEFANeg : VitalDelayType01 := UnitDelay01; -- tPEPE tpd_PGA_PEFANeg : VitalDelayType01 := UnitDelay01; -- tEN/tDIS tpd_CSANeg_A0 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths -- tCLK tperiod_CLKA_posedge : VitalDelayType := UnitDelay; -- tCLKH -- tCLKL tpw_CLKA_posedge : VitalDelayType := UnitDelay; tpw_CLKA_negedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_A0_CLKA : VitalDelayType := UnitDelay; -- tENS tsetup_CSANeg_CLKA : VitalDelayType := UnitDelay; -- tSZS tsetup_SIZ0_CLKB : VitalDelayType := UnitDelay; -- tSWS tsetup_SWB0_CLKB : VitalDelayType := UnitDelay; -- tPGS tsetup_ODDEVEN_CLKA : VitalDelayType := UnitDelay; -- tRSTS tsetup_RSTNeg_CLKA : VitalDelayType := UnitDelay; -- tFSS tsetup_FS0_RSTNeg : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_A0_CLKA : VitalDelayType := UnitDelay; -- tENH thold_CSANeg_CLKA : VitalDelayType := UnitDelay; -- tSZH thold_SIZ0_CLKB : VitalDelayType := UnitDelay; -- tSWH thold_SWB0_CLKB : VitalDelayType := UnitDelay; -- tPGH thold_ODDEVEN_CLKA : VitalDelayType := UnitDelay; -- tRSTH thold_RSTNeg_CLKA : VitalDelayType := UnitDelay; -- tFSH thold_FS0_RSTNeg : VitalDelayType := UnitDelay; -- tskew values: skew times tdevice_SKEW1 : VitalDelayType := UnitDelay; -- Skew Time, between posedge CLKA and posedge CLKB for EFBNeg and FFANeg; -- between posedge CLKC and posedge CLKA for EFANeg and FFCNeg; tdevice_SKEW2 : VitalDelayType := UnitDelay; -- Skew Time, between posedge CLKA and posedge CLKB for AFBNeg and AFANeg; -- between posedge CLKC and posedge CLKA for AFANeg and AFCNeg; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel ); PORT ( A0 : INOUT std_logic; ----------------------------- A1 : INOUT std_logic; -- A2 : INOUT std_logic; -- A3 : INOUT std_logic; -- A4 : INOUT std_logic; -- A5 : INOUT std_logic; -- A6 : INOUT std_logic; -- A7 : INOUT std_logic; -- A8 : INOUT std_logic; -- A9 : INOUT std_logic; -- A10 : INOUT std_logic; -- A11 : INOUT std_logic; -- A12 : INOUT std_logic; -- A13 : INOUT std_logic; -- A14 : INOUT std_logic; -- A15 : INOUT std_logic; -- A16 : INOUT std_logic; -- A17 : INOUT std_logic; -- A18 : INOUT std_logic; -- 36 pin bidirectional Port-A data bus A19 : INOUT std_logic; -- A20 : INOUT std_logic; -- A21 : INOUT std_logic; -- A22 : INOUT std_logic; -- A23 : INOUT std_logic; -- A24 : INOUT std_logic; -- A25 : INOUT std_logic; -- A26 : INOUT std_logic; -- A27 : INOUT std_logic; -- A28 : INOUT std_logic; -- A29 : INOUT std_logic; -- A30 : INOUT std_logic; -- A31 : INOUT std_logic; -- A32 : INOUT std_logic; -- A33 : INOUT std_logic; -- A34 : INOUT std_logic; -- A35 : INOUT std_logic; -------------------------------------- AEANeg : OUT std_logic := 'U'; -- Almost-Empty Flag for Port-A AEBNeg : OUT std_logic := 'U'; -- Almost-Empty Flag for Port-B AFANeg : OUT std_logic := 'U'; -- Almost-Full Flag for Port-A AFCNeg : OUT std_logic := 'U'; -- Almost-Full Flag for Port-C B0 : OUT std_logic; -------------------------------------- B1 : OUT std_logic; -- B2 : OUT std_logic; -- B3 : OUT std_logic; -- B4 : OUT std_logic; -- B5 : OUT std_logic; -- B6 : OUT std_logic; -- B7 : OUT std_logic; -- 18 pin output Port-B data bus B8 : OUT std_logic; -- B9 : OUT std_logic; -- B10 : OUT std_logic; -- B11 : OUT std_logic; -- B12 : OUT std_logic; -- B13 : OUT std_logic; -- B14 : OUT std_logic; -- B15 : OUT std_logic; -- B16 : OUT std_logic; -- B17 : OUT std_logic; -- C0 : IN std_logic; -------------------------------------- C1 : IN std_logic; -- C2 : IN std_logic; -- C3 : IN std_logic; -- C4 : IN std_logic; -- C5 : IN std_logic; -- C6 : IN std_logic; -- C7 : IN std_logic; -- 18 pin input Port-C data bus C8 : IN std_logic; -- C9 : IN std_logic; -- C10 : IN std_logic; -- C11 : IN std_logic; -- C12 : IN std_logic; -- C13 : IN std_logic; -- C14 : IN std_logic; -- C15 : IN std_logic; -- C16 : IN std_logic; -- C17 : IN std_logic; ----------------------------- CLKA : IN std_logic := 'X'; -- Port-A clock CLKB : IN std_logic := 'X'; -- Port-B clock CLKC : IN std_logic := 'X'; -- Port-B clock CSANeg : IN std_logic := 'X'; -- Port-A Chip Select EFANeg : OUT std_logic := 'U'; -- Port-A Empty Flag EFBNeg : OUT std_logic := 'U'; -- Port-B Empty Flag ENA : IN std_logic := 'X'; -- Port-A Enable FFANeg : OUT std_logic := 'U'; -- Port-A Full Flag FFCNeg : OUT std_logic := 'U'; -- Port-A Full Flag FS0 : IN std_logic := 'X'; -- Flag Offset Select FS1 : IN std_logic := 'X'; -- Flag Offset Select ODDEVEN : IN std_logic := 'X'; -- Odd/Even parity select PEFANeg : OUT std_logic := 'U'; -- Port-A Parity Error Flag PEFCNeg : OUT std_logic := 'U'; -- Port-C Parity Error Flag PGA : IN std_logic := 'X'; -- Port-A Parity Generation PGB : IN std_logic := 'X'; -- Port-B Parity Generation RENB : IN std_logic := 'X'; -- Port-B Read Enable RSTNeg : IN std_logic := 'X'; -- Reset SIZ0 : IN std_logic := 'X'; -- Bus Size Select (Ports B and C) SIZ1 : IN std_logic := 'X'; -- Bus Size Select (Ports B and C) SWB0 : IN std_logic := 'X'; -- Port B Byte Swap SWB1 : IN std_logic := 'X'; -- Port B Byte Swap SWC0 : IN std_logic := 'X'; -- Port C Byte Swap SWC1 : IN std_logic := 'X'; -- Port C Byte Swap WRA : IN std_logic := 'X'; -- Port-A Write/Read Select WENC : IN std_logic := 'X' -- Port-C Write Enable ); ATTRIBUTE vital_level0 OF IDT723616 : ENTITY IS True;END IDT723616;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION ----------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral OF IDT723616 IS ATTRIBUTE vital_level0 OF vhdl_behavioral : ARCHITECTURE IS True; CONSTANT partID : String := "IDT723616"; -- delayed inputs and bidirectional ports⌨️ 快捷键说明
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