idt72v821.vhd

VHDL的ram和fifo model code 包含众多的厂家

                  END IF;

                  IF RCLK'Event AND RCLK = '1' THEN

                    IF REN1Neg = '0' AND REN2Neg = '0' AND Pointer > 0 THEN

                        IF Pointer = 1 THEN
                            IF tSKEW_WCLK_RCLK >= tSKEW1 THEN EFNeg_zd <= '0';
                            ELSE EFNeg_zd <= '0' AFTER (tRCLK);
                            END IF;

                            IF tSKEW_WCLK_RCLK >= tSKEW2 THEN PAENeg_zd <= '0';
                            ELSE PAENeg_zd <= '0' AFTER (tRCLK);
                            END IF;

                            IF OENeg = '0' THEN
                                    Q_zd <= FIFOMemory(0);
                            END IF;

                            Pointer <= Pointer - 1;
                            FOR i IN 0 TO Pointer - 1 LOOP
                                    FIFOMemory(i) := FIFOMemory(i + 1);
                            END LOOP;
                        ELSIF Pointer > EmptyOffReg + 1 THEN
                            IF tSKEW_WCLK_RCLK >= tSKEW2 THEN PAENeg_zd <= '1';
                            ELSE PAENeg_zd <= '1' AFTER (tRCLK);
                            END IF;

                            IF tSKEW_WCLK_RCLK >= tSKEW1 THEN EFNeg_zd <= '1';
                            ELSE EFNeg_zd <= '1' AFTER (tRCLK);
                            END IF;

                            IF OENeg = '0' THEN
                                    Q_zd <= FIFOMemory(0);
                            END IF;

                            Pointer <= Pointer - 1;
                            FOR i IN 0 TO Pointer - 1 LOOP
                                    FIFOMemory(i) := FIFOMemory(i + 1);
                            END LOOP;
                        ELSE
                            IF tSKEW_WCLK_RCLK >= tSKEW2 THEN PAENeg_zd <= '0';
                            ELSE PAENeg_zd <= '0' AFTER (tRCLK);
                            END IF;

                            IF tSKEW_WCLK_RCLK >= tSKEW1 THEN EFNeg_zd <= '1';
                            ELSE EFNeg_zd <= '1' AFTER (tRCLK);
                            END IF;EFNeg_zd <= '1';

                            IF OENeg = '0' THEN
                                    Q_zd <= FIFOMemory(0);
                            END IF;

                            Pointer <= Pointer - 1;
                            FOR i IN 0 TO Pointer - 1 LOOP
                                    FIFOMemory(i) := FIFOMemory(i + 1);
                            END LOOP;

                        END IF;
                    ELSIF Pointer = 0 THEN
                            IF tSKEW_WCLK_RCLK >= tSKEW1 THEN EFNeg_zd <= '0';
                            ELSE EFNeg_zd <= '0' AFTER (tRCLK);
                            END IF;

                            IF tSKEW_WCLK_RCLK >= tSKEW2 THEN PAENeg_zd <= '0';
                            ELSE PAENeg_zd <= '0' AFTER (tRCLK);
                            END IF;
                    ELSIF Pointer > EmptyOffReg THEN
                            IF tSKEW_WCLK_RCLK >= tSKEW2 THEN PAENeg_zd <= '1';
                            ELSE PAENeg_zd <= '1' AFTER (tRCLK);
                            END IF;

                            IF tSKEW_WCLK_RCLK >= tSKEW1 THEN EFNeg_zd <= '1';
                            ELSE EFNeg_zd <= '1' AFTER (tRCLK);
                            END IF;
                    ELSE
                            IF tSKEW_WCLK_RCLK >= tSKEW2 THEN PAENeg_zd <= '0';
                            ELSE PAENeg_zd <= '0' AFTER (tRCLK);
                            END IF;

                            IF tSKEW_WCLK_RCLK >= tSKEW1 THEN EFNeg_zd <= '1';
                            ELSE EFNeg_zd <= '1' AFTER (tRCLK);
                            END IF;
                    END IF;

                  END IF;

                  IF OENeg'Event AND OENeg = '1' THEN
                    Q_zd <= ( OTHERS => 'Z' );
                  END IF;

                END IF;
              END PROCESS MainReadWrite;

        SetOffReg: PROCESS( RSNeg, WCLK, RCLK, Pointer )
              BEGIN
                IF RSNeg'Event AND RSNeg = '0' THEN
                          EmptyOffReg <= 7;
                          FullOffReg  <= 7;
                          OffRegSwitch <= 1;
                        ELSIF Start = '1' THEN
                          IF  WCLK'Event AND WCLK = '1' THEN

                            IF WEN1Neg = '0' AND WEN2LDNeg = '0' THEN

                              IF OffRegSwitch = 1 THEN
                                -- EMPTY: Least Significant Bit
                                EmptyOffReg <= to_nat(D(7 DOWNTO 0));
                                OffRegSwitch <= OffRegSwitch + 1;

                              ELSIF OffRegSwitch = 2 THEN
                                -- EMPTY: Most Significant Bit
                                OffRegSwitch <= OffRegSwitch + 1;

                              ELSIF OffRegSwitch = 3 THEN
                                -- FULL: Least Significant Bit
                                    FullOffReg <= to_nat(D(7 DOWNTO 0));
                                OffRegSwitch <= OffRegSwitch + 1;

                              ELSIF OffRegSwitch = 4 THEN
                                -- FULL: Most Significant Bit
                                OffRegSwitch <= 1;

                              END IF;

                            END IF;

                          END IF;


        END IF;
        END PROCESS SetOffReg;

        ------------------------------------------------------------------------
        -- Detection of the actual tSKEW vals                                --
        ------------------------------------------------------------------------

        SkewDetector: PROCESS(RCLK, WCLK)

            VARIABLE tRCLKposedge : Time := 0 ns;
            VARIABLE tWCLKposedge : Time := 0 ns;

        BEGIN

            IF RCLK'event AND RCLK = '1'
            THEN tRCLKposedge := Now;
                 tSKEW_WCLK_RCLK <= Now - tWCLKposedge;
            END IF;

            IF WCLK'event AND WCLK = '1'
            THEN tWCLKposedge := Now;
                 tSKEW_RCLK_WCLK <= Now - tRCLKposedge;
            END IF;

        END PROCESS SkewDetector;

        ------------------------------------------------------------------------
        -- Path delay section                                                 --
        ------------------------------------------------------------------------

        -- path delay for EFNeg

        EFPathDelay: PROCESS (EFNeg_zd)

           VARIABLE EFNeg_GlitchData  : VitalGlitchDataType;

        BEGIN

           VitalPathDelay01
               (OutSignal     => EFNeg,
                OutSignalName => "EFNeg",
                OutTemp       => EFNeg_zd,
                GlitchData    => EFNeg_GlitchData,
                Paths         => (0 => (InputChangeTime => RSNeg'last_event,
                                        PathDelay       => tpd_RSNeg_EFNeg,
                                        PathCondition   => true),
                                  1 => (InputChangeTime => RCLK'last_event,
                                        PathDelay       => tpd_RCLK_EFNeg,
                                        PathCondition   => true)));

        END PROCESS EFPathDelay;

        -- path delay for PAENeg

        PAEPathDelay: PROCESS (PAENeg_zd)

           VARIABLE PAENeg_GlitchData  : VitalGlitchDataType;

        BEGIN

           VitalPathDelay01
               (OutSignal     => PAENeg,
                OutSignalName => "PAENeg",
                OutTemp       => PAENeg_zd,
                GlitchData    => PAENeg_GlitchData,
                Paths         => (0 => (InputChangeTime => RSNeg'last_event,
                                        PathDelay       => tpd_RSNeg_EFNeg,
                                        PathCondition   => true),
                                  1 => (InputChangeTime => RCLK'last_event,
                                        PathDelay       => tpd_RCLK_PAENeg,
                                        PathCondition   => true)));
        END PROCESS PAEPathDelay;

        -- path delay for PAFNeg

        PAFPathDelay: PROCESS (PAFNeg_zd)

           VARIABLE PAFNeg_GlitchData  : VitalGlitchDataType;

        BEGIN

           VitalPathDelay01
               (OutSignal     => PAFNeg,
                OutSignalName => "PAFNeg",
                OutTemp       => PAFNeg_zd,
                GlitchData    => PAFNeg_GlitchData,
                Paths         => (0 => (InputChangeTime => RSNeg'last_event,
                                        PathDelay       => tpd_RSNeg_EFNeg,
                                        PathCondition   => true),
                                  1 => (InputChangeTime => WCLK'last_event,
                                        PathDelay       => tpd_WCLK_PAFNeg,
                                        PathCondition   => true)));

        END PROCESS PAFPathDelay;

        -- path delay for FFNeg

        FFPathDelay: PROCESS (FFNeg_zd)

        VARIABLE FFNeg_GlitchData  : VitalGlitchDataType;

        BEGIN

           VitalPathDelay01
               (OutSignal     => FFNeg,
                OutSignalName => "FFNeg",
                OutTemp       => FFNeg_zd,
                GlitchData    => FFNeg_GlitchData,
                Paths         => (0 => (InputChangeTime => RSNeg'last_event,
                                        PathDelay       => tpd_RSNeg_EFNeg,
                                        PathCondition   => true),
                                  1 => (InputChangeTime => WCLK'last_event,
                                        PathDelay       => tpd_WCLK_FFNeg,
                                        PathCondition   => true)));

        END PROCESS FFPathDelay;

        -- path delay for Q

        QPathDelay_Gen: FOR i IN Q'range GENERATE

            PROCESS (Q_zd(i))

                VARIABLE Q_GlitchData  : VitalGlitchDataType;

            BEGIN

                VitalPathDelay01Z
                    (OutSignal     => Q(i),
                     OutSignalName => "Q",
                     OutTemp       => Q_zd(i),
                     GlitchData    => Q_GlitchData,
                     Paths         => (0 => (InputChangeTime =>RSNeg'last_event,
                                             PathDelay       =>tpd_RSNeg_Q0,
                                             PathCondition   =>true),
                                       1 => (InputChangeTime =>RCLK'last_event,
                                             PathDelay       =>tpd_RCLK_Q0,
                                             PathCondition   =>true),
                                       2 => (InputChangeTime =>OENeg'last_event,
                                             PathDelay       =>tpd_OENeg_Q0,
                                             PathCondition   =>OENeg = '1')));
            END PROCESS;

       END GENERATE QPathDelay_Gen;

    END BLOCK VitalBehavior;

END vhdl_behavioral;