idt72v821.vhd

VHDL的ram和fifo model code 包含众多的厂家

              Violation       => Tviol_REN1Neg_RCLK);
            END IF;

            --8. REN2Neg/RCLK setup/hold time check (tENS, tENH)
            IF REN2Neg'Event AND RCLK'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => REN2Neg,
              TestSignalName  => "REN2Neg",
              RefSignal       => RCLK,
              RefSignalName   => "RCLK",
              SetupLow        => tSetup_REN1Neg_RCLK,
              HoldLow         => tHold_REN1Neg_RCLK,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_REN2Neg_RCLK,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_REN2Neg_RCLK);
            END IF;

            --9. REN1Neg/RSNeg setup time check (tRSS)
            IF REN1Neg'Event AND RSNeg'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => REN1Neg,
              TestSignalName  => "REN1Neg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              SetupLow        => tSetup_REN1Neg_RSNeg,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_REN1Neg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_REN1Neg_RSNeg);
            END IF;

            --10. REN2Neg/RSNeg setup time check (tRSS)
            IF REN2Neg'Event AND RSNeg'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => REN2Neg,
              TestSignalName  => "REN2Neg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              SetupLow        => tSetup_REN1Neg_RSNeg,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_REN2Neg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_REN2Neg_RSNeg);
            END IF;

            --11. WEN1Neg/RSNeg setup time check (tRSS)
            IF WEN1Neg'Event AND RSNeg'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => WEN1Neg,
              TestSignalName  => "WEN1Neg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              SetupLow        => tSetup_REN1Neg_RSNeg,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_WEN1Neg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_WEN1Neg_RSNeg);
            END IF;

            --12. WEN2LDNeg/RSNeg setup time check (tRSS)
            IF WEN2LDNeg'Event AND RSNeg'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => WEN2LDNeg,
              TestSignalName  => "WEN2LDNeg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              SetupLow        => tSetup_REN1Neg_RSNeg,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_WEN2LDNeg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_WEN2LDNeg_RSNeg);
            END IF;

            --13. REN1Neg/RSNeg Recovery time check (tRSR)
            IF REN1Neg'Event AND (RSNeg'Event AND RSNeg = '1') THEN
              VitalRecoveryRemovalCheck (
              TestSignal      => REN1Neg,
              TestSignalName  => "REN1Neg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              Recovery        => tRecovery_REN1Neg_RSNeg,
              ActiveLow       => FALSE,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => RD_REN1Neg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Rviol_REN1Neg_RSNeg);
            END IF;

            --14. REN2Neg/RSNeg Recovery time check (tRSR)
            IF REN2Neg'Event AND RSNeg'Event THEN
            VitalRecoveryRemovalCheck (
              TestSignal      => REN2Neg,
              TestSignalName  => "REN2Neg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              Recovery        => tRecovery_REN1Neg_RSNeg,
              ActiveLow       => FALSE,
              CheckEnabled    => TRUE,
              RefTransition   => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => RD_REN2Neg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Rviol_REN2Neg_RSNeg);
            END IF;

            --15. WEN1Neg/RSNeg Recovery time check (tRSR)
            IF WEN1Neg'Event AND RSNeg'Event THEN
              VitalRecoveryRemovalCheck (
              TestSignal      => WEN1Neg,
              TestSignalName  => "WEN1Neg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              Recovery        => tRecovery_REN1Neg_RSNeg,
              ActiveLow       => FALSE,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => RD_WEN1Neg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Rviol_WEN1Neg_RSNeg);
            END IF;

            --16. WEN2LDNeg/RSNeg Recovery time check (tRSR)
            IF WEN2LDNeg'Event AND RSNeg'Event THEN
            VitalRecoveryRemovalCheck (
              TestSignal      => WEN2LDNeg,
              TestSignalName  => "WEN2LDNeg",
              RefSignal       => RSNeg,
              RefSignalName   => "RSNeg",
              Recovery        => tRecovery_REN1Neg_RSNeg,
              ActiveLow       => FALSE,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => RD_WEN2LDNeg_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Rviol_WEN2LDNeg_RSNeg);
            END IF;

            Violation :=
              Pviol_WCLK            OR
              Pviol_RCLK            OR
              Pviol_RSNeg           OR
              Tviol_D0_WCLK         OR
              Tviol_WEN1Neg_WCLK    OR
              Tviol_WEN2LDNeg_WCLK  OR
              Tviol_REN1Neg_RCLK    OR
              Tviol_REN2Neg_RCLK    OR
              Tviol_WEN1Neg_RSNeg   OR
              Tviol_WEN2LDNeg_RSNeg OR
              Tviol_REN1Neg_RSNeg   OR
              Tviol_REN2Neg_RSNeg   OR
              Rviol_REN1Neg_RSNeg   OR
              Rviol_REN2Neg_RSNeg   OR
              Rviol_WEN1Neg_RSNeg   OR
              Rviol_WEN2LDNeg_RSNeg;

            ASSERT   Violation = '0'
            REPORT   InstancePath & partID & " : signal values may be" &
                     " incorrect due timing violation(s)"
            SEVERITY Warning;

          END IF;

        END PROCESS TimingChecks;

        ---------------------------------------------------------------
        -- Functionality section
        ---------------------------------------------------------------

        MainReadWrite: PROCESS( RSNeg, WCLK, RCLK, WEN1Neg, WEN2LDNeg,
                          REN1Neg, REN2Neg, D, OENeg )

                VARIABLE FIFOMemory : FIFOArray := (FIFOArray'range =>
                                                FIFOWord'(OTHERS => 'X'));
              BEGIN
                IF RSNeg'Event AND RSNeg = '0' THEN
                  FFNeg_zd  <= '1';
                  PAFNeg_zd <= '1';
                  EFNeg_zd  <= '0';
                  PAENeg_zd <= '0';
                  Pointer <= 0;

                  IF OENeg = '0' THEN
                    Q_zd <= (OTHERS => '0');
                  ELSIF OENeg = '1' THEN
                    Q_zd <= (OTHERS => 'Z');
                  END IF;

                  Start <= '1';

                ELSIF Start = '1' THEN
                  IF WCLK'Event AND WCLK = '1' THEN

                    IF WEN1Neg ='0' AND WEN2LDNeg = '1'
                        AND Pointer < FIFOSize THEN

                        IF Pointer = FIFOSize - 1 THEN
                            IF tSKEW_RCLK_WCLK >= tSKEW1 THEN FFNeg_zd <= '0';
                            ELSE FFNeg_zd <= '0' AFTER (tWCLK);
                            END IF;

                            IF tSKEW_RCLK_WCLK >= tSKEW2 THEN PAFNeg_zd <= '0';
                            ELSE PAFNeg_zd <= '0' AFTER (tWCLK);
                            END IF;

                            FIFOMemory( Pointer ) := D;
                            Pointer <= Pointer + 1;
                        ELSIF Pointer >=  FIFOSize - FullOffReg - 1 THEN
                            IF tSKEW_RCLK_WCLK >= tSKEW2 THEN PAFNeg_zd <= '0';
                            ELSE PAFNeg_zd <= '0' AFTER (tWCLK);
                            END IF;

                            IF tSKEW_RCLK_WCLK >= tSKEW1 THEN FFNeg_zd <= '1';
                            ELSE FFNeg_zd <= '1' AFTER (tWCLK);
                            END IF;


                            FIFOMemory( Pointer ) := D;
                            Pointer <= Pointer + 1;
                        ELSE
                            IF tSKEW_RCLK_WCLK >= tSKEW1 THEN FFNeg_zd <= '1';
                            ELSE FFNeg_zd <= '1' AFTER (tWCLK);
                            END IF;

                            IF tSKEW_RCLK_WCLK >= tSKEW2 THEN PAFNeg_zd <= '1';
                            ELSE PAFNeg_zd <= '1' AFTER (tWCLK);
                            END IF;

                            FIFOMemory( Pointer ) := D;
                            Pointer <= Pointer + 1;
                        END IF;
                    ELSIF Pointer = FIFOSize THEN
                            IF tSKEW_RCLK_WCLK >= tSKEW1 THEN FFNeg_zd <= '0';
                            ELSE FFNeg_zd <= '0' AFTER (tWCLK);
                            END IF;

                            IF tSKEW_RCLK_WCLK >= tSKEW2 THEN PAFNeg_zd <= '0';
                            ELSE PAFNeg_zd <= '0' AFTER (tWCLK);
                            END IF;
                    ELSIF Pointer >=  FIFOSize - FullOffReg THEN
                            IF tSKEW_RCLK_WCLK >= tSKEW2 THEN PAFNeg_zd <= '0';
                            ELSE PAFNeg_zd <= '0' AFTER (tWCLK);
                            END IF;

                            IF tSKEW_RCLK_WCLK >= tSKEW1 THEN FFNeg_zd <= '1';
                            ELSE FFNeg_zd <= '1' AFTER (tWCLK);
                            END IF;
                    ELSE
                            IF tSKEW_RCLK_WCLK >= tSKEW1 THEN FFNeg_zd <= '1';
                            ELSE FFNeg_zd <= '1' AFTER (tWCLK);
                            END IF;

                            IF tSKEW_RCLK_WCLK >= tSKEW2 THEN PAFNeg_zd <= '1';
                            ELSE PAFNeg_zd <= '1' AFTER (tWCLK);
                            END IF;

                    END IF;