📄 idt723631.vhd
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SetupHigh => tENS1, SetupLow => tENS1, HoldHigh => tENH1, HoldLow => tENH1, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_ENB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ENB_CLKB); -- MBB/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => MBB, TestSignalName => "MBB", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tENS2, SetupLow => tENS2, HoldHigh => tENH2, HoldLow => tENH2, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_MBB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_MBB_CLKB); -- RSTNeg/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => RSTNeg, TestSignalName => "RSTNeg", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tRSTS, SetupLow => tRSTS, HoldHigh => tRSTH, HoldLow => tRSTH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RSTNeg_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSTNeg_CLKA); -- RSTNeg/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => RSTNeg, TestSignalName => "RSTNeg", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tRSTS, SetupLow => tRSTS, HoldHigh => tRSTH, HoldLow => tRSTH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RSTNeg_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSTNeg_CLKB); -- RTM/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => RTM, TestSignalName => "RTM", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => TRMS, SetupLow => TRMS, HoldHigh => TRMH, HoldLow => TRMH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTM_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTM_CLKB); -- RFM/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => RFM, TestSignalName => "RFM", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => TRMS, SetupLow => TRMS, HoldHigh => TRMH, HoldLow => TRMH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RFM_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RFM_CLKB); -- FSOsD/RSTNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS0SD, TestSignalName => "FS0SD", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS0SD_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS0SD_RSTNeg); -- FS1SEN/RSTNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS1SEN, TestSignalName => "FS1SEN", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS1SEN_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS1SEN_RSTNeg); -- FS0SD/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => FS0SD, TestSignalName => "FS0SD", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tSDS, SetupLow => tSDS, HoldHigh => tSDH, HoldLow => tSDH, CheckEnabled => Offs_Ser_Load_Modeint = '1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS0SD_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS0SD_CLKA); -- FS1SEN/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => FS1SEN, TestSignalName => "FS1SEN", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tSENS, SetupLow => tSENS, HoldHigh => tSENH, HoldLow => tSENH, CheckEnabled => Offs_Ser_Load_Modeint = '1', RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS1SEN_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS1SEN_CLKA); Violation := Pviol_CLKA OR Pviol_CLKB OR Tviol_A0_CLKA OR TViol_B0_CLKB OR Tviol_CSANeg_CLKA OR Tviol_WRA_CLKA OR Tviol_ENA_CLKA OR Tviol_MBA_CLKA OR Tviol_CSBNeg_CLKB OR Tviol_WRB_CLKB OR Tviol_ENB_CLKB OR Tviol_MBB_CLKB OR Tviol_RSTNeg_CLKA OR Tviol_RSTNeg_CLKB OR Tviol_FS0SD_RSTNeg OR Tviol_FS1SEN_RSTNeg OR Tviol_FS0SD_CLKA OR Tviol_FS1SEN_CLKA OR Tviol_RFM_CLKB OR Tviol_RTM_CLKB ; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorret due timing violation(s)" SEVERITY Warning; END IF; END PROCESS TimingChecks;---------------------------------------------------------------------------------- Functionality Section ---------------------------------------------------------------------------------- ------------------------------------------------------------------------------ -- Reset ------------------------------------------------------------------------------ -- Initial Reset - ------------------------------------------------------------------------------ Init_Reset: PROCESS (RSTNeg) BEGIN IF (RSTNeg = '0') THEN MRSDoneint <= '1'; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Internal Reset Signal ------------------------------------------------------------------------------ Internal_Reset: PROCESS (RSTNeg,MRSDoneint) BEGIN IF (MRSDoneint = '1') THEN RST1int<=RSTNeg AND MRSDoneint; END IF; END PROCESS; ------------------------------------------------------------------------------ -- Count Clocks during RSTNeg ------------------------------------------------------------------------------ Count_CLK1: PROCESS (CLKA, CLKB, RST1int) BEGIN IF RST1int'Event THEN IF (RST1int = '0')OR (RST1int'LAST_VALUE = '0') THEN IF RST1int'LAST_VALUE = '0' THEN IF (CountCLKA1int < 4) OR (CountCLKB1int < 4) THEN ASSERT FALSE REPORT InstancePath & partID & ": During RESET should be 4 posedges on CLKA, CLKB"; END IF; END IF; CountCLKA1int <= 0; CountCLKB1int <= 0; END IF; ELSIF MRSDoneint = '1' THEN IF CLKA'EVENT AND CLKA = '1' THEN IF Offs_Ser_Load_Modeint = '0' THEN IF CountCLKA1int < 4 THEN CountCLKA1int <= CountCLKA1int + 1; END IF; ELSE IF (CountLoadOffsetint = Offs_Ser_Number - 1) AND (FS1SEN = '0') THEN -- Current CLKA is the last while Offset Loading CountCLKA1int <= 1; END IF; END IF; END IF; IF CLKB'EVENT AND CLKB = '1' THEN IF CountCLKB1int < 4 THEN CountCLKB1int <= CountCLKB1int + 1; END IF; END IF; END IF; END PROCESS Count_CLK1 ; ------------------------------------------------------------------------------ -- Load Almost-Empty / Almost-Full Offsets ------------------------------------------------------------------------------ Store_Almost_Flags_Offs: PROCESS (RST1int, CLKA)-------MRSint--?????? VARIABLE Offs: NATURAL RANGE 0 TO FIFOSize-4; VARIABLE FS: std_logic_vector(1 DOWNTO 0); VARIABLE FlagStart: Boolean; BEGIN -- Fixed Offset for FIFO IF RST1int'Event AND (RST1int = '1') AND (RST1int'LAST_VALUE = '0') THEN FS := (FS1SEN & FS0SD); IF (FS /= "00") THEN CASE FS IS WHEN "01" => Offs := 8; WHEN "10" => Offs := 64; WHEN OTHERS => NULL; END CASE; X1int <= Offs; Y1int <= Offs; END IF; END IF; -- Set Parallel/Serial Offset Loading Mode IF RST1int'Event AND (RST1int = '1') AND (RST1int'LAST_VALUE = '0') THEN FS := (FS1SEN & FS0SD); IF (FS = "00") THEN Offs_Par_Load_Modeint <= '1'; CountLoadOffsetint <= 0; ELSIF (FS = "11")THEN Offs_Ser_Load_Modeint <= '1'; CountLoadOffsetint <= 0; FlagStart := False; END IF; END IF; -- Parallel Offset Loading Mode IF Offs_Par_Load_Modeint = '1' THEN IF CLKA'EVENT AND CLKA = '1' THEN IF (ENA = '1') AND (CountCLKA1int >= 2) THEN------------ zathem 2??-?? CountLoadOffsetint <= CountLoadOffsetint + 1; CASE CountLoadOffsetint IS WHEN 0 => Y1int <= to_nat(A_ipd); WHEN 1 => X1int <= to_nat(A_ipd); Offs_Par_Load_Modeint <= '0'; IF (Y1int=0 )OR (Y1int>Offs_Val_Limit)THEN ASSERT FALSE REPORT InstancePath & partID & " Invalid Offset Value loaded"; END IF; WHEN OTHERS => NULL; END CAS⌨️ 快捷键说明
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