idt723631.vhd

VHDL的ram和fifo model code 包含众多的厂家

    SIGNAL ReadPtr1_l_int_add : std_logic; 
    
    ----------------------------------------------------------------------------
    -- Internal Signals for AFA/AEA/AFB/AEB FLAGS implementation according
    -- to IDT Verilog gate-level model simulation 
    
    SIGNAL IRHdl2 : STD_LOGIC;
    SIGNAL UniEnl : STD_LOGIC := '1';
    -- SIGNAL BM : STD_LOGIC := '0'; -- external input port 
    SIGNAL BEFWFTl : STD_LOGIC;
    
    SIGNAL MRSTl1, PRSTl1 : STD_LOGIC;
    
    SIGNAL Rd_Ptr1, Wr_Ptr1 : STD_LOGIC_VECTOR (FIFOPOWER -1 DOWNTO 0);
    
    SIGNAL AFlGen_A, AF1l_A, AF2l_A, AFlA : STD_LOGIC; 
    SIGNAL RcvEn_AF_A, BCmpEn_AF_A : STD_LOGIC;
    
    SIGNAL AElGen_B, AE1l_B, AE2l_B, AElB : STD_LOGIC; 
    SIGNAL RcvEn_AE_B, BCmpEn_AE_B : STD_LOGIC;
    
    SIGNAL AF_A, AE_B : STD_LOGIC_VECTOR (FIFOPOWER - 1 DOWNTO 0);
  
  BEGIN -- VitalBehavior block
     
--------------------------------------------------------------------------------
-- Timing Check Section                                                         
--------------------------------------------------------------------------------

     TimingChecks: PROCESS ( A_ipd, B_ipd,   CLKA, CLKB, CSANeg, CSBNeg,
       ENA, ENB, FS0SD, FS1SEN, MBA, MBB,  RFM , RTM ,RSTNeg,
         WRA, WRB)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;

    -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_B0_CLKB       : X01 := '0';
      VARIABLE TD_B0_CLKB          : VitalTimingDataType;

      VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENA_CLKA      : X01 := '0';
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_MBA_CLKA      : X01 := '0';
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_CSBNeg_CLKB   : X01 := '0';
      VARIABLE TD_CSBNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_WRB_CLKB      : X01 := '0';
      VARIABLE TD_WRB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_ENB_CLKB      : X01 := '0';
      VARIABLE TD_ENB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_MBB_CLKB      : X01 := '0';
      VARIABLE TD_MBB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_RSTNeg_CLKA  : X01 := '0';
      VARIABLE TD_RSTNeg_CLKA     : VitalTimingDataType;

    
      VARIABLE Tviol_RSTNeg_CLKB  : X01 := '0';
      VARIABLE TD_RSTNeg_CLKB     : VitalTimingDataType;
    
      VARIABLE Tviol_FS0SD_RSTNeg : X01 := '0';
      VARIABLE TD_FS0SD_RSTNeg    : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_RSTNeg: X01 := '0';
      VARIABLE TD_FS1SEN_RSTNeg   : VitalTimingDataType;
      
      VARIABLE Tviol_FS0SD_CLKA    : X01 := '0';
      VARIABLE TD_FS0SD_CLKA       : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_CLKA   : X01 := '0';
      VARIABLE TD_FS1SEN_CLKA      : VitalTimingDataType;

      
      VARIABLE Tviol_RFM_CLKB   : X01 := '0';
      VARIABLE TD_RFM_CLKB      : VitalTimingDataType;
      
      VARIABLE Tviol_RTM_CLKB   : X01 := '0';
      VARIABLE TD_RTM_CLKB      : VitalTimingDataType;

    -- Violation variable (used to OR all individual violation variables)

      VARIABLE Violation           : X01 := '0';
    
BEGIN

--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------
 IF  (TimingChecksOn)
 THEN

      -- CLKA period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKA,
          TestSignalName  => "CLKA",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKA);

      -- CLKB period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKB,
          TestSignalName  => "CLKB",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKB);

      -- A/CLKA setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => A_ipd,
          TestSignalName  => "A",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSANeg = '0') AND (WRA = '1') 
                              AND (ENA = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_A0_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_A0_CLKA);

   -- B/CLKB setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => B_ipd,
          TestSignalName  => "B",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSBNeg = '0') AND (WRB = '0') 
                              AND (ENB = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_B0_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => TViol_B0_CLKB);


      -- CSANeg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSANeg,
          TestSignalName  => "CSANeg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupLow        => tENS2,
          SetupHigh       => tENS2,
          HoldLow         => tENH2,
          HoldHigh        => tENH2,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSANeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSANeg_CLKA);

      -- WRA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRA,
          TestSignalName  => "WRA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS2,
          SetupLow        => tENS2,
          HoldHigh        => tENH2,
          HoldLow         => tENH2,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRA_CLKA);

      -- ENA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENA,
          TestSignalName  => "ENA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS1,
          SetupLow        => tENS1,
          HoldHigh        => tENH1,
          HoldLow         => tENH1,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENA_CLKA);

      -- MBA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBA,
          TestSignalName  => "MBA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS2,
          SetupLow        => tENS2,
          HoldHigh        => tENH2,
          HoldLow         => tENH2,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBA_CLKA);

      -- CSBNeg/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSBNeg,
          TestSignalName  => "CSBNeg",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupLow        => tENS2,
          SetupHigh       => tENS2,
          HoldLow         => tENH2,
          HoldHigh        => tENH2,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSBNeg_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSBNeg_CLKB);

      -- WRB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRB,
          TestSignalName  => "WRB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS2,
          SetupLow        => tENS2,
          HoldHigh        => tENH2,
          HoldLow         => tENH2,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRB_CLKB);

      -- ENB/CLKB setup/hold time check

      VitalSetupHoldCheck (    -----------------------!
          TestSignal      => ENB,
          TestSignalName  => "ENB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS1,
          SetupLow        => tENS1,
          HoldHigh        => tENH1,
          HoldLow         => tENH1,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENB_CLKB);

      -- MBB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBB,
          TestSignalName  => "MBB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS2,
          SetupLow        => tENS2,
          HoldHigh        => tENH2,
          HoldLow         => tENH2,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBB_CLKB);

      -- ENB/CLKB setup/hold time check

      VitalSetupHoldCheck (-------------------------------2
          TestSignal      => ENB,
          TestSignalName  => "ENB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",