idt723632.vhd

VHDL的ram和fifo model code 包含众多的厂家

          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_RST1Neg_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_RST1Neg_CLKB);
            
  --------------------------------------------------------------------------- 
         
      -- FS0/RST1Neg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS0,
          TestSignalName  => "FS0",
          RefSignal       => RST1Neg,
          RefSignalName   => "RST1Neg",
          SetupHigh       => tsetup_FS0_RST1Neg,
          SetupLow        => tsetup_FS0_RST1Neg,
          HoldHigh        => thold_FS0_RST1Neg,
          HoldLow         => thold_FS0_RST1Neg,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS0_RST1Neg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS0_RST1Neg);

      -- FS1/RST1Neg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS1,
          TestSignalName  => "FS1",
          RefSignal       => RST1Neg,
          RefSignalName   => "RST1Neg",
          SetupHigh       => tsetup_FS1_RST1Neg,
          SetupLow        => tsetup_FS1_RST1Neg,
          HoldHigh        => thold_FS1_RST1Neg,
          HoldLow         => thold_FS1_RST1Neg,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS1_RST1Neg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS1_RST1Neg);
        
      -- FS0/RST2Neg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS0,
          TestSignalName  => "FS0",
          RefSignal       => RST2Neg,
          RefSignalName   => "RST2Neg",
          SetupHigh       => tsetup_FS0_RST2Neg,
          SetupLow        => tsetup_FS0_RST2Neg,
          HoldHigh        => thold_FS0_RST2Neg,
          HoldLow         => thold_FS0_RST2Neg,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS0_RST2Neg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS0_RST2Neg);

      -- FS1/RST2Neg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS1,
          TestSignalName  => "FS1",
          RefSignal       => RST2Neg,
          RefSignalName   => "RST2Neg",
          SetupHigh       => tsetup_FS1_RST2Neg,
          SetupLow        => tsetup_FS1_RST2Neg,
          HoldHigh        => thold_FS1_RST2Neg,
          HoldLow         => thold_FS1_RST2Neg,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS1_RST2Neg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS1_RST2Neg);
        
  Violation := Pviol_CLKA          OR
               Pviol_CLKB          OR
              
               Tviol_A0_CLKA       OR
               Tviol_B0_CLKB       OR
               
               Tviol_CSANeg_CLKA   OR
               Tviol_CSBNeg_CLKB   OR
                
               Tviol_WRA_CLKA   OR
               Tviol_WRB_CLKB   OR
               
                Tviol_ENA_CLKA      OR               
               Tviol_ENB_CLKB       OR
              
               Tviol_MBA_CLKA       OR               
               Tviol_MBB_CLKB       OR
                             
               Tviol_RST1Neg_CLKA   OR                
               Tviol_RST2Neg_CLKA   OR
               Tviol_RST1Neg_CLKB   OR
               Tviol_RST2Neg_CLKB   OR
               
               Tviol_FS0_RST1Neg    OR
               Tviol_FS1_RST1Neg    OR
               Tviol_FS0_RST2Neg    OR
               Tviol_FS1_RST2Neg;
               
                ASSERT   Violation = '0'
                REPORT   InstancePath & partID & " : signal values may be" &
                         " incorret due timing violation(s)"
                SEVERITY Warning;
  END IF;
  
END PROCESS TimingChecks;

--------------------------------------------------------------------------------
-- Functionality Section
--------------------------------------------------------------------------------
-- Chosing programming method and setting value 0ffset registers 
-- X1int, X2int, Y1int, Y2int
--------------------------------------------------------------------------------
-- Master reset  prepare
-------------------------------------------------------------------------
 Rst1OrRst2<=RST1Neg OR RST2Neg;
           
 Rst1AndRst2<=RST1Neg  AND RST2Neg;
----------------------------------------------------- --------------------------
 -- Master RESET   in state 0 at the simultaneuos RST1Neg,RST2Neg=0
------------------------------------------------------------------------------- 
  Master_RESET : PROCESS (Rst1OrRst2,Rst1AndRst2 )
 BEGIN
 
  IF (Rst1OrRst2'Event AND Rst1OrRst2='0') THEN
          MasterReset<='0';  MasterResetWase <='1';  
 
  ELSIF(Rst1AndRst2'Event AND Rst1AndRst2='1' AND MasterReset='0' )THEN
          MasterReset<='1'; 
   END IF;
   
 END PROCESS;
 -----------------------------------------------------------------------------
 --  Programming  offset register Y1int ( for almost empty flag port BA, AFANeg)
 ---------------------------------------------------------------------------- 
    Story_Almost_Flags_Offs_Y1int: PROCESS (CLKA,RST1Neg )
      VARIABLE FS: std_logic_vector(1 DOWNTO 0); 
    BEGIN
     IF RST1Neg'Event AND RST1Neg = '1' AND MasterResetWase ='1' THEN 
         FS := (FS1 & FS0);
      
      CASE FS IS
        WHEN "00"	=> NULL;
        WHEN "01" 	=>  Y1int <= 8;
        WHEN "10" 	=> Y1int <= 16;
        WHEN "11" 	=> Y1int <= 64;
        WHEN OTHERS 	=> NULL;
      END CASE;
      ELSIF  CLKA'EVENT AND CLKA = '1'  THEN
        IF (IRA_zd = '1') AND (ENA = '1') AND (CSANeg = '0') 
         AND (ProgrOffsetint= '1' )
         AND (MBA  = '0') AND (WRA = '1') AND (CountWrCLKAint= 0)THEN
          Y1int<= to_nat( A_ipd(FIFOPOWER-1 downto 0)) ; 
                               --  convert t0 natural, length variable!!
        END IF;
     END IF;
   END PROCESS;
   
   ------------------------------------------------------------------------
 --  Programming  offset register X1int ( for almost empty flagport B, AEBNeg)
  ---------------------------------------------------------------------------- 
    Story_Almost_Flags_Offs_X1int: PROCESS (CLKA,RST1Neg )
     VARIABLE FS: std_logic_vector(1 DOWNTO 0);
    BEGIN
     IF RST1Neg'Event AND RST1Neg = '1'  AND MasterResetWase ='1' THEN
        FS := (FS1 & FS0);
      CASE FS IS
        WHEN "00"	=> NULL;
        WHEN "01" 	=>  X1int <= 8;
        WHEN "10" 	=> X1int <= 16;
        WHEN "11" 	=> X1int <= 64;
        WHEN OTHERS 	=> NULL;
      END CASE;
     ELSIF  CLKA'EVENT AND CLKA = '1'  THEN
      IF (IRA_zd = '1') AND (ENA = '1') AND (CSANeg = '0')
        AND (ProgrOffsetint= '1' )AND (MBA  = '0')
          AND (WRA = '1')AND(CountWrCLKAint= 1)THEN
          X1int<=  to_nat( A_ipd(FIFOPOWER-1 downto 0)) ;
                                        --  convert, length variable!!
      END IF;
     END IF;
   END PROCESS;        
     
  ----------------------------------------------------------------------
  -- Programming  offset register Y2int ( for almost empty flag port BA, AFANeg)
  ---------------------------------------------------------------------------- 
    Story_Almost_Flags_Offs_Y2int: PROCESS (CLKA,RST2Neg)
     VARIABLE FS: std_logic_vector(1 DOWNTO 0);
    BEGIN
     IF RST2Neg'Event AND RST2Neg = '1' AND MasterResetWase ='1' THEN
      FS := (FS1 & FS0); 
      CASE FS IS
        WHEN "00"	=> NULL;
        WHEN "01" 	=>  Y2int <= 8;
        WHEN "10" 	=> Y2int <= 16;
        WHEN "11" 	=> Y2int <= 64;
        WHEN OTHERS 	=> NULL;
      END CASE;
     ELSIF  CLKA'EVENT AND CLKA = '1'  THEN
      IF (IRA_zd = '1') AND (ENA = '1') AND (CSANeg = '0') 
        AND (ProgrOffsetint= '1' )AND (MBA  = '0')
          AND (WRA = '1')AND(CountWrCLKAint= 2)THEN
          Y2int<=   to_nat( A_ipd(FIFOPOWER-1 downto 0));
                                --  to convert, length variable!!
      END IF;
     END IF;
   END PROCESS;
 -------------------------------------------------------------------------------
 --   Programming  offset register X2int ( for almost empty flag port A, AEANeg)
 ---------------------------------------------------------------------------- 
    Story_Almost_Flags_Offs_X2int: PROCESS (CLKA,RST2Neg)
     VARIABLE FS: std_logic_vector(1 DOWNTO 0);
    BEGIN
     IF RST2Neg'Event AND RST2Neg = '1'AND MasterResetWase ='1' THEN
       FS := (FS1 & FS0);
      CASE FS IS
        WHEN "00"	=> NULL;
        WHEN "01" 	=>  X2int <= 8;
        WHEN "10" 	=> X2int <= 16;
        WHEN "11" 	=> X2int <= 64;
        WHEN OTHERS 	=> NULL;
      END CASE;
     ELSIF  CLKA'EVENT AND CLKA = '1'  THEN
      IF (IRA_zd = '1') AND (ENA = '1') AND (CSANeg = '0')
          AND (ProgrOffsetint= '1' )AND (MBA  = '0')
          AND (WRA = '1')AND(CountWrCLKAint= 3)THEN
          X2int<=  to_nat( A_ipd(FIFOPOWER-1 downto 0));       ----- it need to convert, length variable!!
      END IF;
     END IF;
   END PROCESS;
-----------------------------------------------------------------------
--Drive Programming offset regime inicator ProgrOffsetint
------------------------------------------------------------------
  Drive_ProgrOffsetint:PROCESS (CountWrCLKAint,  MasterReset)
  VARIABLE FS: std_logic_vector(1 DOWNTO 0);
  
   BEGIN
    IF  MasterResetWase'event AND MasterResetWase='1' THEN
             ProgrOffsetint<= '0';
   ELSIF  MasterReset'EVENT AND MasterReset='1'    THEN
           FS := (FS1 & FS0);
     
         IF  FS="00" THEN
           ProgrOffsetint<= '1';
  
         END IF;
  
   ELSIF CountWrCLKAint>= 4 THEN
   
       ProgrOffsetint<= '0';
  
   END IF;
 END PROCESS; 
-----------------------------------------------------------------------
--  CountWrCLKAint -after Master Reset and (FS1,FS0)=00
-----------------------------------------------------------------------
Drive_CountWrCLKAint: PROCESS (CLKA,  ProgrOffsetint)
 BEGIN                     
           IF (ProgrOffsetint'EVENT AND ProgrOffsetint='1') THEN
              CountWrCLKAint<=0;
           END IF;		    	  
       
       IF CLKA'EVENT AND CLKA = '1' THEN---
       
           IF (ENA = '1') AND (CSANeg = '0') AND (WRA = '1')
            AND (ProgrOffsetint='1')AND (CountWrCLKAint <= 5   )
            AND (MBA  = '0') AND (IRA_zd  = '1')
                                                 THEN
                                                 
                  CountWrCLKAint <= CountWrCLKAint + 1;
          
          END IF;
       END IF;  
             
 END PROCESS;  
------------------------------------------------------------------------- 
-- Count Clocks during RST1Neg is active
------------------------------------------------------------------------------
  
  Drive_CLKA: PROCESS (CLKA, RST1Neg, RST2Neg)
  BEGIN
    IF RST1Neg'Event THEN
       IF RST1Neg = '0' THEN  
          CountCLKAint <= 0;
                   
       ELSIF RST1Neg = '1' THEN
          IF (CountCLKAint < 4) OR (CountCLKBint < 4)  THEN
	    	ASSERT FALSE REPORT InstancePath & partID & 
	    	  "During RESET should be 4 posedges on CLKA , CLKB"; 
	  END IF;
	  CountCLKAint <= 0;		    	  
       END IF;
    END IF;                 
     IF RST2Neg'Event THEN
       IF RST2Neg = '0' THEN  
          CountCLKAint <= 0;
       	    	  
       END IF;
    END IF;
      
       IF CLKA'EVENT AND ( CLKA = '1' )AND (CountCLKAint <= 10) 
                    AND MasterResetWase ='1' THEN
           
          CountCLKAint <= CountCLKAint + 1;  
       
       END IF;   

  END PROCESS;   
     
 Drive_CLKB: PROCESS (CLKB,  RST2Neg,RST1Neg)
  BEGIN
    IF RST2Neg'Event THEN
       IF RST2Neg = '0' THEN  
          C