idt723632.vhd

VHDL的ram和fifo model code 包含众多的厂家

    
    IRA      : OUT    std_logic := 'U'; -- Input  A ready flag
    IRB      : OUT   std_logic := 'U'; --Input  B ready flag
    MBA      : IN    std_logic := 'X'; -- Port-A Mailbox Select
    MBB      : IN    std_logic := 'X'; -- Port-B Mailbox Select
    
    MBF1Neg  : OUT   std_logic := 'U'; -- Mail1 Register Flag
    MBF2Neg  : OUT   std_logic := 'U'; -- Mail2 Register Flag
     ORA     : OUT   std_logic := 'U'; -- Output A ready Flag
     ORB     : OUT   std_logic := 'U'; -- Output B ready Flag
   RST1Neg   : IN    std_logic := 'X'; --  FIFO1 Reset
   RST2Neg   : IN    std_logic := 'X'; --  FIFO1 Reset
     WRA  : IN    std_logic := 'X'; -- Port-A Write/Read Select
    WRB   : IN    std_logic := 'X'  -- Port-B Write/Read Select
        
     );
   PORT MAP (
    A_ipd(0)    => A0_ipd,
    A_ipd(1)    => A1_ipd,
    A_ipd(2)    => A2_ipd,
    A_ipd(3)    => A3_ipd,
    A_ipd(4)    => A4_ipd,
    A_ipd(5)    => A5_ipd,
    A_ipd(6)    => A6_ipd,
    A_ipd(7)    => A7_ipd,
    A_ipd(8)    => A8_ipd,
    A_ipd(9)    => A9_ipd,
    A_ipd(10)   => A10_ipd,
    A_ipd(11)   => A11_ipd,
    A_ipd(12)   => A12_ipd,
    A_ipd(13)   => A13_ipd,
    A_ipd(14)   => A14_ipd,
    A_ipd(15)   => A15_ipd,
    A_ipd(16)   => A16_ipd,
    A_ipd(17)   => A17_ipd,
    A_ipd(18)   => A18_ipd,
    A_ipd(19)   => A19_ipd,
    A_ipd(20)   => A20_ipd,
    A_ipd(21)   => A21_ipd,
    A_ipd(22)   => A22_ipd,
    A_ipd(23)   => A23_ipd,
    A_ipd(24)   => A24_ipd,
    A_ipd(25)   => A25_ipd,
    A_ipd(26)   => A26_ipd,
    A_ipd(27)   => A27_ipd,
    A_ipd(28)   => A28_ipd,
    A_ipd(29)   => A29_ipd,
    A_ipd(30)   => A30_ipd,
    A_ipd(31)   => A31_ipd,
    A_ipd(32)   => A32_ipd,
    A_ipd(33)   => A33_ipd,
    A_ipd(34)   => A34_ipd,
    A_ipd(35)   => A35_ipd,
    A(0)    	=> A0,
    A(1)    	=> A1,
    A(2)    	=> A2,
    A(3)    	=> A3,
    A(4) 	=> A4,
    A(5)  	=> A5,
    A(6)  	=> A6,
    A(7)    	=> A7,
    A(8)    	=> A8,
    A(9)    	=> A9,
    A(10)   	=> A10,
    A(11)   	=> A11,
    A(12)   	=> A12,
    A(13)   	=> A13,
    A(14)   	=> A14,
    A(15)   	=> A15,
    A(16)   	=> A16,
    A(17)   	=> A17,
    A(18)   	=> A18,
    A(19)   	=> A19,
    A(20)   	=> A20,
    A(21)   	=> A21,
    A(22)   	=> A22,
    A(23)   	=> A23,
    A(24)   	=> A24,
    A(25)   	=> A25,
    A(26)   	=> A26,
    A(27)   	=> A27,
    A(28)   	=> A28,
    A(29)   	=> A29,
    A(30)   	=> A30,
    A(31)   	=> A31,
    A(32)   	=> A32,
    A(33)   	=> A33,
    A(34)   	=> A34,
    A(35)    	=> A35,
    AEANeg  	=> AEANeg,
    AEBNeg   	=> AEBNeg,
    AFANeg   	=> AFANeg,
    AFBNeg   	=> AFBNeg,
    
    B_ipd(0)    => B0_ipd,
    B_ipd(1)    => B1_ipd,
    B_ipd(2)    => B2_ipd,
    B_ipd(3)    => B3_ipd,
    B_ipd(4)    => B4_ipd,
    B_ipd(5)    => B5_ipd,
    B_ipd(6)    => B6_ipd,
    B_ipd(7)    => B7_ipd,
    B_ipd(8)    => B8_ipd,
    B_ipd(9)    => B9_ipd,
    B_ipd(10)   => B10_ipd,
    B_ipd(11)   => B11_ipd,
    B_ipd(12)   => B12_ipd,
    B_ipd(13)   => B13_ipd,
    B_ipd(14)   => B14_ipd,
    B_ipd(15)   => B15_ipd,
    B_ipd(16)   => B16_ipd,
    B_ipd(17)   => B17_ipd,
    B_ipd(18)   => B18_ipd,
    B_ipd(19)   => B19_ipd,
    B_ipd(20)   => B20_ipd,
    B_ipd(21)   => B21_ipd,
    B_ipd(22)   => B22_ipd,
    B_ipd(23)   => B23_ipd,
    B_ipd(24)   => B24_ipd,
    B_ipd(25)   => B25_ipd,
    B_ipd(26)   => B26_ipd,
    B_ipd(27)   => B27_ipd,
    B_ipd(28)   => B28_ipd,
    B_ipd(29)   => B29_ipd,
    B_ipd(30)   => B30_ipd,
    B_ipd(31)   => B31_ipd,
    B_ipd(32)   => B32_ipd,
    B_ipd(33)   => B33_ipd,
    B_ipd(34)   => B34_ipd,
    B_ipd(35)   => B35_ipd ,
    B(0)       	=> B0,
    B(1)       	=> B1,
    B(2)       	=> B2,
    B(3)       	=> B3,
    B(4)       	=> B4,
    B(5)       	=> B5,
    B(6)       	=> B6,
    B(7)       	=> B7,
    B(8)       	=> B8,
    B(9)       	=> B9,
    B(10)      	=> B10,
    B(11)      	=> B11,
    B(12)      	=> B12,
    B(13)      	=> B13,
    B(14)      	=> B14,
    B(15)      	=> B15,
    B(16)      	=> B16,
    B(17)      	=> B17, 
     B(18)   	=> B18,
    B(19)   	=> B19,
    B(20)   	=> B20,
    B(21)   	=> B21,
    B(22)   	=> B22,
    B(23)   	=> B23,
    B(24)   	=> B24,
    B(25)   	=> B25,
    B(26)   	=> B26,
    B(27)   	=> B27,
    B(28)   	=> B28,
    B(29)   	=> B29,
    B(30)   	=> B30,
    B(31)   	=> B31,
    B(32)   	=> B32,
    B(33)   	=> B33,
    B(34)   	=> B34,
    B(35)    	=> B35,
    CLKA        => CLKA_ipd,
    CLKB        => CLKB_ipd,
   
    CSANeg   =>CSANeg_ipd,
    CSBNeg   =>CSBNeg_ipd,
    
    ENA     =>  ENA_ipd, 
    ENB     => ENB_ipd,  
   
    FS0    =>  FS0_ipd, 
    FS1    =>  FS1_ipd,
    
    IRA     =>IRA , --outputs
    IRB      =>IRB, 
    MBA     =>MBA_ipd, 
    MBB      =>MBB_ipd, 
   MBF1Neg =>MBF1Neg,
   MBF2Neg =>MBF2Neg,
   
     ORA     => ORA, 
     ORB    =>ORB, 
   RST1Neg   => RST1Neg_ipd, 
   RST2Neg  => RST2Neg_ipd,
     WRA =>  WRA_ipd,
    WRB  => WRB_ipd);
        
  -- zero delayed outputs and bidirectional ports 
  -- (func. sec. uses these signals instead of =
  --  actual outputs and bidirectional ports);
  -- actual outputs are assigned in Path Delay Section
     SIGNAL A_zd        : std_logic_vector (35 downto 0);
     SIGNAL B_zd         : std_logic_vector (35  downto 0);
   
     SIGNAL AEANeg_zd    :    std_logic; 
     SIGNAL AEBNeg_zd    :    std_logic; 
     SIGNAL AFANeg_zd    :    std_logic ;
     SIGNAL AFBNeg_zd    :    std_logic ;  
     SIGNAL IRA_zd       :    std_logic ; -- Input  A ready flag
     SIGNAL IRB_zd       :    std_logic ; --Input  B ready flag
     SIGNAL MBF1Neg_zd   :    std_logic ; -- Mail1 Register Flag
     SIGNAL MBF2Neg_zd   :    std_logic ; -- Mail2 Register Flag
     SIGNAL ORA_zd       :    std_logic ; -- Output A ready Flag
     SIGNAL ORB_zd       :    std_logic ; -- Output B ready Flag
    
 -- 11111111111111111111111111111111111111111111111111111111111111111111
---------------------------------------------------------------------
 -- FIFO memory definitions
------------------------------------------------------------------------- 
  -- general
  CONSTANT   FIFOPOWER    : positive := 9;
  CONSTANT   FIFOSIZE     : positive := 2**FIFOPOWER;
  CONSTANT FIFOWordLength : positive := 36; -- number of bits in SRAM word
  SUBTYPE  FIFOWord IS Std_Logic_Vector(FIFOWordLength - 1 DOWNTO 0);
  TYPE FIFOArray IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord;
  CONSTANT partID : String := "IDT723632";
  
  ------------------------------------------------------------------------------
  -- internal signals 
  ------------------------------------------------------------------------------  
  
  -- FIFO Arrays
  
     SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
     SIGNAL FIFOMemory2int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
                                        
  -- Main Registers                                       
  
     -- Input Registers
       
     SIGNAL InputReg1int   : FIFOWord := (OTHERS => 'X');
     SIGNAL InputReg2int   : FIFOWord := (OTHERS => 'X'); 
     
     -- Output Registers
      
     SIGNAL OutputReg1int  : FIFOWord := (OTHERS => 'X');
     SIGNAL OutputReg2int  : FIFOWord := (OTHERS => 'X');
     
     -- FIFO Pointers
     
     SIGNAL ReadPtr1int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL ReadPtr2int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr1int   : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr2int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- FIFO Offset for Almoust Empty/Full Flags --controlled  by FS0,FS1
     
     SIGNAL X1int,X2int,Y1int,Y2int : Natural RANGE 0 TO FIFOSize-1;
     
     -- Flags Flip-flop first stage (each flag is synchonized 
     -- to its Port Clock through two flip-flop stages)
    ----Internal Signals    
     SIGNAL IRA1int,AFA1int,ORB1int,ORB2int,
            AEB1int,ORA1int,ORA2int,
            AEA1int,IRB1int,AFB1int ,AFB2int  : std_logic;
     SIGNAL  OutputReg1Readyint,OutputReg2Readyint: std_logic;
 
   
    --Mail registers
      SIGNAL   MAIL1int  :FIFOWord := (OTHERS => 'X');
      SIGNAL   MAIL2int  :FIFOWord := (OTHERS => 'X');
          
    -- Flags "Input Register is loaded" - in this 
     -- model they will be loaded to FIFOMemory on CLK negedge      
      
     SIGNAL InputReg1Readyint   : std_logic; 
     SIGNAL InputReg2Readyint   : std_logic; 
  
     -- Counters of Clocks during RST1Neg, RST2Neg is active
     
     SIGNAL CountCLKAint, CountCLKBint,CountWrCLKAint: Natural;
     
    --signals for Master Reset
     
       SIGNAL MasterReset,Rst1OrRst2,Rst1AndRst2,ProgrOffsetint : std_logic;
       
      SIGNAL MasterResetWase : std_logic :='0'; 
--------------------------------------------------------------------------------
  BEGIN -- VitalBehavior block
--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------

     TimingChecks: PROCESS ( A_ipd, B_ipd, CLKA, CLKB,  CSANeg,CSBNeg, ENA,ENB,
     MBA,MBB, FS0, FS1,     RST1Neg,RST2Neg,  WRA, WRB)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;
  
      -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';     --------A
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_B0_CLKB       : X01 := '0';    ------------B
      VARIABLE TD_B0_CLKB          : VitalTimingDataType;
  ---------------------------------------------------------tab0-1,tens
    VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';        --------A
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';      --------A
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;
      
       VARIABLE Tviol_CSBNeg_CLKB   : X01 := '0';  ------------B
      VARIABLE TD_CSBNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_WRB_CLKB      : X01 := '0';   ------------B
      VARIABLE TD_WRB_CLKB         : VitalTimingDataType;
    -------------------------------------------------------------------  
      VARIABLE Tviol_ENA_CLKA      : X01 := '0';--------A
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENB_CLKB     : X01 := '0'; ------------B
      VARIABLE TD_ENB_CLKB        : VitalTimingDataType;
      
      VARIABLE Tviol_MBA_CLKA      : X01 := '0';--------A
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;