idt72v241.ftm
来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 108 行
FTM
108 行
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT72V241 Parts</TITLE><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 99 JUN 21 Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT72V241<FMFTIME>IDT72V241L10J<SOURCE>IDT data sheet February 1999</SOURCE>IDT72V241L10PF<SOURCE>IDT data sheet February 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK Q0 (2:5:6.5) (2:5:6.5) (2:5:6.5) (0:5:6.5) (2:5:6.5) (0:5:6.5)) (IOPATH RSNeg Q0 (2:7:10) (2:7:10) (2:7:10) (2:7:10) (2:7:10) (2:7:10)) (IOPATH RSNeg EFNeg (2:7:10) (2:7:10)) (IOPATH OENeg Q0 () () (3:6:9) (0:6:9) (3:6:9) (0:6:9)) (IOPATH WCLK FFNeg (2:4:6.5) (2:4:6.5)) (IOPATH RCLK EFNeg (2:4:6.5) (2:4:6.5)) (IOPATH RCLK PAENeg (2:4:6.5) (2:4:6.5)) (IOPATH WCLK PAFNeg (2:4:6.5) (2:4:6.5)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (10)) (PERIOD (posedge WCLK) (10)) (WIDTH (posedge RCLK) (4.5)) (WIDTH (negedge RCLK) (4.5)) (SETUPHOLD D0 WCLK (3) (0.5)) (SETUPHOLD REN1Neg RCLK (3) (0.5)) (WIDTH (negedge RSNeg) (10)) (SETUP REN1Neg RSNeg (8)) (RECOVERY REN1Neg RSNeg (8)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (5) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (14) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72V241L15J<SOURCE>IDT data sheet February 1999</SOURCE>IDT72V241L15PF<SOURCE>IDT data sheet February 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK Q0 (2:7:10) (2:7:10) (3:6:8) (0:6:8) (3:6:8) (0:6:8)) (IOPATH RSNeg Q0 (3:8:15) (3:8:15) (3:8:15) (3:8:15) (3:8:15) (3:8:15)) (IOPATH RSNeg EFNeg (3:8:15) (3:8:15)) (IOPATH OENeg Q0 () () (3:6:8) (0:6:8) (3:6:8) (0:6:8)) (IOPATH WCLK FFNeg (3:6:10) (3:6:10)) (IOPATH RCLK EFNeg (3:6:10) (3:6:10)) (IOPATH RCLK PAENeg (3:6:10) (3:6:10)) (IOPATH WCLK PAFNeg (3:6:10) (3:6:10)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (15)) (PERIOD (posedge WCLK) (15)) (WIDTH (posedge RCLK) (6)) (WIDTH (negedge RCLK) (6)) (SETUPHOLD D0 WCLK (4) (1)) (SETUPHOLD REN1Neg RCLK (4) (1)) (WIDTH (negedge RSNeg) (15)) (SETUP REN1Neg RSNeg (10)) (RECOVERY REN1Neg RSNeg (10)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (6) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (18) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72V241L20J<SOURCE>IDT data sheet February 1999</SOURCE>IDT72V241L20PF<SOURCE>IDT data sheet February 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK Q0 (2:8:12) (2:8:12) (3:7:10) (0:7:10) (3:7:10) (0:7:10)) (IOPATH RSNeg Q0 (3:12:20) (3:12:20) (3:12:20) (3:12:20) (3:12:20) (3:12:20)) (IOPATH RSNeg EFNeg (3:12:20) (3:12:20)) (IOPATH OENeg Q0 () () (3:7:10) (0:7:10) (3:7:10) (0:7:10)) (IOPATH WCLK FFNeg (3:8:12) (3:8:12)) (IOPATH RCLK EFNeg (3:8:12) (3:8:12)) (IOPATH RCLK PAENeg (3:8:12) (3:8:12)) (IOPATH WCLK PAFNeg (3:8:12) (3:8:12)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (20)) (PERIOD (posedge WCLK) (20)) (WIDTH (posedge RCLK) (8)) (WIDTH (negedge RCLK) (8)) (SETUPHOLD D0 WCLK (5) (1)) (SETUPHOLD REN1Neg RCLK (5) (1)) (WIDTH (negedge RSNeg) (20)) (SETUP REN1Neg RSNeg (12)) (RECOVERY REN1Neg RSNeg (12)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (8) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (20) ) ) )</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?