idt72t36135m.vhd

VHDL的ram和fifo model code 包含众多的厂家

                TmpOffset (CountForSerial) := FWFT ;
            ELSE
                SerLdOk := no;
            END IF;
            CountForSerial := CountForSerial + 1;
            IF CountForSerial = 38 THEN
                SerLdEnd := yes;
                CountForSerial := 0;
            END IF;
        END SerialLoad;

        PROCEDURE ParallelRead
        IS
        BEGIN

            TmpMemLocOE := TmpMemLocRead;
            SetFlagForOE;
            IF ReadByteOffset = LSBEmptyOffset AND EnReadOffs = yes THEN
                TmpOffsetRead := to_slv(EmptyOffset,19);
                TmpMemLocRead (15 DOWNTO 0) := TmpOffsetRead (15 DOWNTO 0);
                ReadByteOffset := MSBEmptyOffset;
                EnReadOffs := no;
            ELSIF ReadByteOffset = MSBEmptyOffset AND EnReadOffs = yes THEN
                TmpOffsetRead := to_slv(EmptyOffset,19);
                TmpMemLocRead (2 DOWNTO 0) := TmpOffsetRead (18 DOWNTO 16);
                ReadByteOffset := LSBFullOffset;
                EnReadOffs := no;
            ELSIF ReadByteOffset = LSBFullOffset AND EnReadOffs = yes THEN
                TmpOffsetRead := to_slv(FullOffset,19);
                TmpMemLocRead (15 DOWNTO 0) := TmpOffsetRead (15 DOWNTO 0);
                ReadByteOffset := MSBFullOffset;
                EnReadOffs := no;
            ELSIF ReadByteOffset = MSBFullOffset AND EnReadOffs = yes THEN
                TmpOffsetRead := to_slv(FullOffset,19);
                TmpMemLocRead (2 DOWNTO 0) := TmpOffsetRead (18 DOWNTO 16);
                ReadByteOffset := LSBEmptyOffset;
                EnReadOffs := no;
            END IF;
        END ParallelRead;

        BEGIN

            --------------------------------
            -- Timing Check Section
            --------------------------------
            IF (TimingChecksON) THEN

            -- WCLK pulse ( low&high ) width and period check - Syn
                VitalPeriodPulseCheck (
                  TestSignal      => WCLK,
                  TestSignalName  => "WCLK",
                  Period          => tperiod_WCLK_SYN_EQ_1_posedge,
                  PulseWidthHigh  => tpw_WCLK_SYN_EQ_1_posedge,
                  PulseWidthLow   => tpw_WCLK_SYN_EQ_1_negedge,
                  CheckEnabled    => ASYWNeg='1',
                  HeaderMsg       => InstancePath & partID,
                  PeriodData      => PD_WCLK_SYN,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Pviol_WCLK_SYN);

            -- WCLK pulse ( low&high ) width and period check - Asyn
                VitalPeriodPulseCheck (
                  TestSignal      => WCLK,
                  TestSignalName  => "WCLK",
                  Period          => tperiod_WCLK_ASYN_EQ_1_posedge,
                  PulseWidthHigh  => tpw_WCLK_ASYN_EQ_1_posedge,
                  PulseWidthLow   => tpw_WCLK_ASYN_EQ_1_negedge,
                  CheckEnabled    => ASYWNeg='0',
                  HeaderMsg       => InstancePath & partID,
                  PeriodData      => PD_WCLK_ASYN,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Pviol_WCLK_ASYN);

            -- RCLK pulse ( low&high ) width and period check - Syn
                VitalPeriodPulseCheck (
                  TestSignal      => RCLK,
                  TestSignalName  => "RCLK",
                  Period          => tperiod_RCLK_SYN_EQ_1_posedge,
                  PulseWidthHigh  => tpw_RCLK_SYN_EQ_1_posedge,
                  PulseWidthLow   => tpw_RCLK_SYN_EQ_1_negedge,
                  CheckEnabled    => ASYRNeg='1',
                  HeaderMsg       => InstancePath & partID,
                  PeriodData      => PD_RCLK_SYN,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Pviol_RCLK_SYN);

            -- RCLK pulse ( low&high ) width and period check - Asyn
                VitalPeriodPulseCheck (
                  TestSignal      => RCLK,
                  TestSignalName  => "RCLK",
                  Period          => tperiod_RCLK_ASYN_EQ_1_posedge,
                  PulseWidthHigh  => tpw_RCLK_ASYN_EQ_1_posedge,
                  PulseWidthLow   => tpw_RCLK_ASYN_EQ_1_negedge,
                  CheckEnabled    => ASYRNeg='0',
                  HeaderMsg       => InstancePath & partID,
                  PeriodData      => PD_RCLK_ASYN,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Pviol_RCLK_ASYN);

            -- SCLK pulse ( low&high ) width and period check
                VitalPeriodPulseCheck (
                  TestSignal      => SCLK,
                  TestSignalName  => "SCLK",
                  Period          => tperiod_SCLK_posedge,
                  PulseWidthHigh  => tpw_SCLK_posedge,
                  PulseWidthLow   => tpw_SCLK_negedge,
                  CheckEnabled    => TRUE,
                  HeaderMsg       => InstancePath & partID,
                  PeriodData      => PD_SCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Pviol_SCLK);

            --  MRSNeg pulse low width check
                VitalPeriodPulseCheck (
                  TestSignal      => MRSNeg,
                  TestSignalName  => "MRSNeg",
                  PulseWidthLow   => tpw_MRSNeg_negedge,
                  CheckEnabled    => TRUE,
                  HeaderMsg       => InstancePath & partID,
                  PeriodData      => PD_MRSNeg,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Pviol_MRSNeg);

            --  PRSNeg pulse low width check
                VitalPeriodPulseCheck (
                  TestSignal      => PRSNeg,
                  TestSignalName  => "PRSNeg",
                  PulseWidthLow   => tpw_PRSNeg_negedge,
                  CheckEnabled    => TRUE,
                  HeaderMsg       => InstancePath & partID,
                  PeriodData      => PD_PRSNeg,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Pviol_PRSNeg);

            -- DIn/WCLK setup/hold time check
                VitalSetupHoldCheck (
                  TestSignal      => DIn,
                  TestSignalName  => "DIn",
                  RefSignal       => WCLK,
                  RefSignalName   => "WCLK",
                  SetupHigh       => tsetup_D0_WCLK,
                  SetupLow        => tsetup_D0_WCLK,
                  HoldHigh        => thold_D0_WCLK,
                  HoldLow         => thold_D0_WCLK,
                  CheckEnabled    => TRUE,
                  RefTransition    => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_DIn_WCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_DIn_WCLK);

            -- FWFT/SCLK setup/hold time check
                VitalSetupHoldCheck (
                  TestSignal      => FWFT,
                  TestSignalName  => "FWFT",
                  RefSignal       => SCLK,
                  RefSignalName   => "SCLK",
                  SetupHigh       => tsetup_FWFT_SCLK,
                  SetupLow        => tsetup_FWFT_SCLK,
                  HoldHigh        => thold_FWFT_SCLK,
                  HoldLow         => thold_FWFT_SCLK,
                  CheckEnabled    => SENNeg='0',
                  RefTransition    => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_FWFT_SCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_FWFT_SCLK);

             -- WENNeg/WCLK setup/hold time check
                VitalSetupHoldCheck (
                  TestSignal      => WENNeg,
                  TestSignalName  => "WENNeg",
                  RefSignal       => WCLK,
                  RefSignalName   => "WCLK",
                  SetupLow        => tsetup_WENNeg_WCLK,
                  HoldLow         => thold_WENNeg_WCLK,
                  CheckEnabled    => TRUE,
                  RefTransition   => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_WENNeg_WCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_WENNeg_WCLK);

            -- RENNeg/RCLK setup/hold time check
                VitalSetupHoldCheck (
                  TestSignal      => RENNeg,
                  TestSignalName  => "RENNeg",
                  RefSignal       => RCLK,
                  RefSignalName   => "RCLK",
                  SetupLow        => tsetup_RENNeg_RCLK,
                  HoldLow         => thold_RENNeg_RCLK,
                  CheckEnabled    => TRUE,
                  RefTransition   => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_RENNeg_RCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_RENNeg_RCLK);

            -- RENNeg/RCLK setup time check
                VitalSetupHoldCheck (
                  TestSignal      => RENNeg,
                  TestSignalName  => "RENNeg",
                  RefSignal       => RCLK,
                  RefSignalName   => "RCLK",
                  SetupHigh       => tsetup_RENNeg_RCLK,
                  CheckEnabled    => RTNeg='0',
                  RefTransition   => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_RENNeg_RCLK_RT,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_RENNeg_RCLK_RT);

            -- WENNeg/RCLK setup time check
                VitalSetupHoldCheck (
                  TestSignal      => WENNeg,
                  TestSignalName  => "WENNeg",
                  RefSignal       => RCLK,
                  RefSignalName   => "RCLK",
                  SetupHigh       => tsetup_WENNeg_RCLK,
                  CheckEnabled    => RTNeg='0',
                  RefTransition   => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_WENNeg_RCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_WENNeg_RCLK);

            -- MARK/RCLK setup time check
                VitalSetupHoldCheck (
                  TestSignal      => MARK,
                  TestSignalName  => "MARK",
                  RefSignal       => RCLK,
                  RefSignalName   => "RCLK",
                  SetupHigh       => tsetup_MARK_RCLK,
                  CheckEnabled    => TRUE,
                  RefTransition   => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_MARK_RCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_MARK_RCLK);

            -- SENNeg/SCLK setup/hold time check
                VitalSetupHoldCheck (
                  TestSignal      => SENNeg,
                  TestSignalName  => "SENNeg",
                  RefSignal       => SCLK,
                  RefSignalName   => "SCLK",
                  SetupLow        => tsetup_SENNeg_SCLK,
                  HoldLow         => thold_SENNeg_SCLK,
                  CheckEnabled    => TRUE,
                  RefTransition   => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_SENNeg_SCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_SENNeg_SCLK);

            -- RTNeg/RCLK setup/hold time check
                VitalSetupHoldCheck (
                  TestSignal      => RTNeg,
                  TestSignalName  => "RTNeg",
                  RefSignal       => RCLK,
                  RefSignalName   => "RCLK",
                  SetupLow        => tsetup_RTNeg_RCLK,
                  HoldLow         => thold_RTNeg_RCLK,
                  CheckEnabled    => TRUE,
                  RefTransition   => '/',
                  HeaderMsg       => InstancePath & partID,
                  TimingData      => TD_RTNeg_RCLK,
                  XOn             => XOn,
                  MsgOn           => MsgOn,
                  Violation       => Tviol_RTNeg_RCLK);

            -- LDNeg/RCLK setup/hold time check