idt72t36135m.vhd

VHDL的ram和fifo model code 包含众多的厂家

        EF1Neg     : OUT  std_ulogic := 'U'; --  Empty Flag1
        EF2Neg     : OUT  std_ulogic := 'U'; --  Empty Flag2
        FF1Neg     : OUT  std_ulogic := 'U'; --  Full Flag1
        FF2Neg     : OUT  std_ulogic := 'U'; --  Full Flag2
        PAE1Neg    : OUT  std_ulogic := 'U'; --  Programmable Almost Empty Flag1
        PAE2Neg    : OUT  std_ulogic := 'U'; --  Programmable Almost Empty Flag2
        PAF1Neg    : OUT  std_ulogic := 'U'; --  Programmable Almost Full Flag1
        PAF2Neg    : OUT  std_ulogic := 'U'; --  Programmable Almost Full Flag2

        Q0        : OUT std_logic := 'Z';  --
        Q1        : OUT std_logic := 'Z';  --
        Q2        : OUT std_logic := 'Z';  --
        Q3        : OUT std_logic := 'Z';  --
        Q4        : OUT std_logic := 'Z';  --  Data Output Bus
        Q5        : OUT std_logic := 'Z';  --
        Q6        : OUT std_logic := 'Z';  --
        Q7        : OUT std_logic := 'Z';  --
        Q8        : OUT std_logic := 'Z';  --
        Q9        : OUT std_logic := 'Z';  --
        Q10        : OUT std_logic := 'Z';  --
        Q11        : OUT std_logic := 'Z';  --
        Q12        : OUT std_logic := 'Z';  --
        Q13        : OUT std_logic := 'Z';  --
        Q14        : OUT std_logic := 'Z';  --  Data Output Bus
        Q15        : OUT std_logic := 'Z';  --
        Q16        : OUT std_logic := 'Z';  --
        Q17        : OUT std_logic := 'Z';  --
        Q18        : OUT std_logic := 'Z';  --
        Q19        : OUT std_logic := 'Z';  --
        Q20        : OUT std_logic := 'Z';  --
        Q21        : OUT std_logic := 'Z';  --
        Q22        : OUT std_logic := 'Z';  --
        Q23        : OUT std_logic := 'Z';  --
        Q24        : OUT std_logic := 'Z';  --  Data Output Bus
        Q25        : OUT std_logic := 'Z';  --
        Q26        : OUT std_logic := 'Z';  --
        Q27        : OUT std_logic := 'Z';  --
        Q28        : OUT std_logic := 'Z';  --
        Q29        : OUT std_logic := 'Z';  --
        Q30        : OUT std_logic := 'Z';  --
        Q31        : OUT std_logic := 'Z';  --
        Q32        : OUT std_logic := 'Z';  --
        Q33        : OUT std_logic := 'Z';  --
        Q34        : OUT std_logic := 'Z';  --  Data Output Bus
        Q35        : OUT std_logic := 'Z');  --

        ATTRIBUTE vital_level0 OF idt72t36135m : ENTITY IS True;

END idt72t36135m;

        -----------------------------------------------------------------------
        --  ARCHITECTURE DECLARATION
        -----------------------------------------------------------------------

ARCHITECTURE vhdl_behavioral OF idt72t36135m IS

    ATTRIBUTE vital_level0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID : String := "idt72t36135m";

    -- delayed inputs
    SIGNAL D0_ipd        : std_ulogic := 'U';
    SIGNAL D1_ipd        : std_ulogic := 'U';
    SIGNAL D2_ipd        : std_ulogic := 'U';
    SIGNAL D3_ipd        : std_ulogic := 'U';
    SIGNAL D4_ipd        : std_ulogic := 'U';
    SIGNAL D5_ipd        : std_ulogic := 'U';
    SIGNAL D6_ipd        : std_ulogic := 'U';
    SIGNAL D7_ipd        : std_ulogic := 'U';
    SIGNAL D8_ipd        : std_ulogic := 'U';
    SIGNAL D9_ipd        : std_ulogic := 'U';
    SIGNAL D10_ipd        : std_ulogic := 'U';
    SIGNAL D11_ipd        : std_ulogic := 'U';
    SIGNAL D12_ipd        : std_ulogic := 'U';
    SIGNAL D13_ipd        : std_ulogic := 'U';
    SIGNAL D14_ipd        : std_ulogic := 'U';
    SIGNAL D15_ipd        : std_ulogic := 'U';
    SIGNAL D16_ipd        : std_ulogic := 'U';
    SIGNAL D17_ipd        : std_ulogic := 'U';
    SIGNAL D18_ipd        : std_ulogic := 'U';
    SIGNAL D19_ipd        : std_ulogic := 'U';
    SIGNAL D20_ipd        : std_ulogic := 'U';
    SIGNAL D21_ipd        : std_ulogic := 'U';
    SIGNAL D22_ipd        : std_ulogic := 'U';
    SIGNAL D23_ipd        : std_ulogic := 'U';
    SIGNAL D24_ipd        : std_ulogic := 'U';
    SIGNAL D25_ipd        : std_ulogic := 'U';
    SIGNAL D26_ipd        : std_ulogic := 'U';
    SIGNAL D27_ipd        : std_ulogic := 'U';
    SIGNAL D28_ipd        : std_ulogic := 'U';
    SIGNAL D29_ipd        : std_ulogic := 'U';
    SIGNAL D30_ipd        : std_ulogic := 'U';
    SIGNAL D31_ipd        : std_ulogic := 'U';
    SIGNAL D32_ipd        : std_ulogic := 'U';
    SIGNAL D33_ipd        : std_ulogic := 'U';
    SIGNAL D34_ipd        : std_ulogic := 'U';
    SIGNAL D35_ipd        : std_ulogic := 'U';

    SIGNAL ASYRNeg_ipd    : std_ulogic := 'U';
    SIGNAL ASYWNeg_ipd    : std_ulogic := 'U';
    SIGNAL FSEL0_ipd      : std_ulogic := 'U';
    SIGNAL FSEL1_ipd      : std_ulogic := 'U';
    SIGNAL FWFT_ipd       : std_ulogic := 'U';
    SIGNAL LDNeg_ipd      : std_ulogic := 'U';
    SIGNAL MARK_ipd       : std_ulogic := 'U';
    SIGNAL OENeg_ipd      : std_ulogic := 'U';
    SIGNAL MRSNeg_ipd     : std_ulogic := 'U';
    SIGNAL PFM_ipd        : std_ulogic := 'U';
    SIGNAL PRSNeg_ipd     : std_ulogic := 'U';
    SIGNAL RCLK_ipd       : std_ulogic := 'U';
    SIGNAL RENNeg_ipd     : std_ulogic := 'U';
    SIGNAL RCSNeg_ipd     : std_ulogic := 'U';
    SIGNAL RTNeg_ipd      : std_ulogic := 'U';
    SIGNAL SENNeg_ipd     : std_ulogic := 'U';
    SIGNAL SCLK_ipd       : std_ulogic := 'U';
    SIGNAL WCLK_ipd       : std_ulogic := 'U';
    SIGNAL WENNeg_ipd     : std_ulogic := 'U';
    SIGNAL WCSNeg_ipd     : std_ulogic := 'U';

    -- FIFO memory definations
    CONSTANT TotalLoc      : positive := 524287;
    CONSTANT DataWidth     : positive := 36;
    CONSTANT MaxData       : positive := 262143;

    -- SKEW stuff (see also generics list)
    ALIAS  tSKEW1          : VitalDelayType IS tdevice_SKEW1;
    ALIAS  tSKEW2          : VitalDelayType IS tdevice_SKEW2;
    ALIAS  tRPE            : VitalDelayType IS tdevice_RPE;
    SIGNAL BufIn, BufOut   : std_logic;

    SIGNAL Const0          : std_logic := '0';
    SIGNAL Const1          : std_logic := '1';

    TYPE SyncAsync IS (Synchronous, Asynchronous);

    SHARED VARIABLE FromOE      : BOOLEAN;
    SHARED VARIABLE FromRCLK    : BOOLEAN;
    SHARED VARIABLE ProgFlagMode   : SyncAsync;

    SIGNAL EFNeg_zd        : std_logic_vector(1 TO 2);
    SIGNAL FFNeg_zd        : std_logic_vector(1 TO 2);
    SIGNAL QOut_zd         : std_logic_vector(35 DOWNTO 0);
    SIGNAL PAENeg_zd       : std_logic_vector(1 TO 2);
    SIGNAL PAFNeg_zd       : std_logic_vector(1 TO 2);

BEGIN

     --------------------------------------------------------------
     -- Dummy instances for exporting tSKEW vals from SDF file
     -- using DEVICE construct
     --------------------------------------------------------------

     SKEW1: VitalBuf (BufOut, BufIn, (tdevice_SKEW2, tdevice_SKEW2));

     SKEW2: VitalBuf (BufOut, BufIn, (tdevice_SKEW2, tdevice_SKEW2));

     RPE:   VitalBuf (BufOut, BufIn, (tdevice_RPE, tdevice_RPE));

    -------------------------------------------------------------------
    -- Wire Delays
    -------------------------------------------------------------------
    WireDelay: BLOCK
    BEGIN

        w_1:  VitalWireDelay (D0_ipd       , D0       , tipd_D0        );
        w_2:  VitalWireDelay (D1_ipd       , D1       , tipd_D1        );
        w_3:  VitalWireDelay (D2_ipd       , D2       , tipd_D2        );
        w_4:  VitalWireDelay (D3_ipd       , D3       , tipd_D3        );
        w_5:  VitalWireDelay (D4_ipd       , D4       , tipd_D4        );
        w_6:  VitalWireDelay (D5_ipd       , D5       , tipd_D5        );
        w_7:  VitalWireDelay (D6_ipd       , D6       , tipd_D6        );
        w_8:  VitalWireDelay (D7_ipd       , D7       , tipd_D7        );
        w_9:  VitalWireDelay (D8_ipd       , D8       , tipd_D8        );
        w_10: VitalWireDelay (D9_ipd       , D9       , tipd_D9        );
        w_11: VitalWireDelay (D10_ipd      , D10      , tipd_D10       );
        w_12: VitalWireDelay (D11_ipd      , D11      , tipd_D11       );
        w_13: VitalWireDelay (D12_ipd      , D12      , tipd_D12       );
        w_14: VitalWireDelay (D13_ipd      , D13      , tipd_D13       );
        w_15: VitalWireDelay (D14_ipd      , D14      , tipd_D14       );
        w_16: VitalWireDelay (D15_ipd      , D15      , tipd_D15       );
        w_17: VitalWireDelay (D16_ipd      , D16      , tipd_D16       );
        w_18: VitalWireDelay (D17_ipd      , D17      , tipd_D17       );
        w_19: VitalWireDelay (D18_ipd      , D18      , tipd_D18       );
        w_20: VitalWireDelay (D19_ipd      , D19      , tipd_D19       );
        w_21: VitalWireDelay (D20_ipd      , D20      , tipd_D20       );
        w_22: VitalWireDelay (D21_ipd      , D21      , tipd_D21       );
        w_23: VitalWireDelay (D22_ipd      , D22      , tipd_D22       );
        w_24: VitalWireDelay (D23_ipd      , D23      , tipd_D23       );
        w_25: VitalWireDelay (D24_ipd      , D24      , tipd_D24       );
        w_26: VitalWireDelay (D25_ipd      , D25      , tipd_D25       );
        w_27: VitalWireDelay (D26_ipd      , D26      , tipd_D26       );
        w_28: VitalWireDelay (D27_ipd      , D27      , tipd_D27       );
        w_29: VitalWireDelay (D28_ipd      , D28      , tipd_D28       );
        w_30: VitalWireDelay (D29_ipd      , D29      , tipd_D29       );
        w_31: VitalWireDelay (D30_ipd      , D30      , tipd_D30       );
        w_32: VitalWireDelay (D31_ipd      , D31      , tipd_D31       );
        w_33: VitalWireDelay (D32_ipd      , D32      , tipd_D32       );
        w_34: VitalWireDelay (D33_ipd      , D33      , tipd_D33       );
        w_35: VitalWireDelay (D34_ipd      , D34      , tipd_D34       );
        w_36: VitalWireDelay (D35_ipd      , D35      , tipd_D35       );
        w_37: VitalWireDelay (ASYRNeg_ipd  , ASYRNeg  , tipd_ASYRNeg   );
        w_38: VitalWireDelay (ASYWNeg_ipd  , ASYWNeg  , tipd_ASYWNeg   );
        w_39: VitalWireDelay (FSEL0_ipd    , FSEL0    , tipd_FSEL0     );
        w_40: VitalWireDelay (FSEL1_ipd    , FSEL1    , tipd_FSEL1     );
        w_41: VitalWireDelay (FWFT_ipd     , FWFT     , tipd_FWFT      );
        w_42: VitalWireDelay (LDNeg_ipd    , LDNeg    , tipd_LDNeg     );
        w_43: VitalWireDelay (MARK_ipd     , MARK     , tipd_MARK      );
        w_44: VitalWireDelay (OENeg_ipd    , OENeg    , tipd_OENeg     );
        w_45: VitalWireDelay (MRSNeg_ipd   , MRSNeg   , tipd_MRSNeg    );
        w_46: VitalWireDelay (PRSNeg_ipd   , PRSNeg   , tipd_PRSNeg    );
        w_47: VitalWireDelay (PFM_ipd      , PFM      , tipd_PFM       );
        w_48: VitalWireDelay (RCLK_ipd     , RCLK     , tipd_RCLK      );
        w_49: VitalWireDelay (RENNeg_ipd   , RENNeg   , tipd_RENNeg    );
        w_50: VitalWireDelay (RCSNeg_ipd   , RCSNeg   , tipd_RCSNeg    );
        w_51: VitalWireDelay (RTNeg_ipd    , RTNeg    , tipd_RTNeg     );
        w_52: VitalWireDelay (SENNeg_ipd   , SENNeg   , tipd_SENNeg    );
        w_53: VitalWireDelay (SCLK_ipd     , SCLK     , tipd_SCLK      );
        w_54: VitalWireDelay (WCLK_ipd     , WCLK     , tipd_WCLK      );
        w_55: VitalWireDelay (WENNeg_ipd   , WENNeg   , tipd_WENNeg    );
        w_56: VitalWireDelay (WCSNeg_ipd   , WCSNeg   , tipd_WCSNeg    );

    END BLOCK WireDelay;

    -------------------------------------------------------------------
    --  Main behavior Block
    -------------------------------------------------------------------

    Main: BLOCK

        PORT (
            DIn     : IN  std_logic_vector( 35 DOWNTO 0):= (OTHERS=>'U');

            ASYRNeg  : IN  std_ulogic := 'U';
            ASYWNeg  : IN  std_ulogic := 'U';
            FSEL0    : IN  std_ulogic := 'U';
            FSEL1    : IN  std_ulogic := 'U';
            FWFT     : IN  std_ulogic := 'U';
            LDNeg    : IN  std_ulogic := 'U';
            MARK     : IN  std_ulogic := 'U';
            OENeg    : IN  std_ulogic := 'U';
            MRSNeg   : IN  std_ulogic := 'U';
            PRSNeg   : IN  std_ulogic := 'U';
            PFM      : IN  std_ulogic := 'U';
            RCLK     : IN  std_ulogic := 'U';
            RENNeg   : IN  std_ulogic := 'U';
            RCSNeg   : IN  std_ulogic := 'U';
            RTNeg    : IN  std_ulogic := 'U';
            SENNeg   : IN  std_ulogic := 'U';
            SCLK     : IN  std_ulogic := 'U';
            WCLK     : IN  std_ulogic := 'U';
            WENNeg   : IN  std_ulogic := 'U';
            WCSNeg   : IN  std_ulogic := 'U';

            QOut     : OUT std_logic_vector( 35 DOWNTO 0) := (OTHERS=>'Z');

            EFNeg    : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U');
            FFNeg    : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U');
            PAENeg   : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U');
            PAFNeg   : OUT std_logic_vector(1 TO 2) := (OTHERS => 'U')
            );

        PORT MAP (
            DIn(0)          => D0_ipd,
            DIn(1)          => D1_ipd,
            DIn(2)          => D2_ipd,
            DIn(3)          => D3_ipd,
            DIn(4)          => D4_ipd,
            DIn(5)          => D5_ipd,
            DIn(6)          => D6_ipd,
            DIn(7)          => D7_ipd,
            DIn(8)          => D8_ipd,
            DIn(9)          => D9_ipd,
            DIn(10)         => D10_ipd,
            DIn(11)         => D11_ipd,
            DIn(12)         => D12_ipd,
            DIn(13)         => D13_ipd,
            DIn(14)         => D14_ipd,
            DIn(15)         => D15_ipd,
            DIn(16)         => D16_ipd,
            DIn(17)         => D17_ipd,
            DIn(18)         => D18_ipd,
            DIn(19)         => D19_ipd,
            DIn(20)         => D20_ipd,
            DIn(21)         => D21_ipd,
            DIn(22)         => D22_ipd,
            DIn(23)         => D23_ipd,
            DIn(24)         => D24_ipd,
            DIn(25)         => D25_ipd,
            DIn(26)         => D26_ipd,
            DIn(27)         => D27_ipd,
            DIn(28)         => D28_ipd,