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📄 idt72t36135m.vhd

📁 VHDL的ram和fifo model code 包含众多的厂家
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----------------------------------------------------------------------------------  File Name: idt72t36135m.vhd----------------------------------------------------------------------------------  Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.----  MODIFICATION HISTORY:----  version: | author:    | mod date: | changes made:--   V1.0      A.Anic       05 Dec 12   Initial release------------------------------------------------------------------------------------  PART DESCRIPTION:----  Library:     FIFO--  Technology:  CMOS--  Part:        idt72t36135m--  Description: 18Mb (524,288 x 36) High-Speed FIFO ----------------------------------------------------------------------------------  Known Bugs:------------------------------------------------------------------------------------------------------------------------------------------------------------------LIBRARY ieee;    USE ieee.vital_primitives.ALL;                 USE ieee.vital_timing.ALL;                 USE ieee.std_logic_1164.ALL;LIBRARY fmf;     USE fmf.gen_utils.ALL;                 USE fmf.conversions.to_nat;                 USE fmf.conversions.to_slv;--------------------------------------------------------------------------------- ENTITY DECLARATION-------------------------------------------------------------------------------ENTITY idt72t36135m IS    GENERIC (        -- tipd delays: interconnect path delays        tipd_D0           : VitalDelayType01  := VitalZeroDelay01;        tipd_D1           : VitalDelayType01  := VitalZeroDelay01;        tipd_D2           : VitalDelayType01  := VitalZeroDelay01;        tipd_D3           : VitalDelayType01  := VitalZeroDelay01;        tipd_D4           : VitalDelayType01  := VitalZeroDelay01;        tipd_D5           : VitalDelayType01  := VitalZeroDelay01;        tipd_D6           : VitalDelayType01  := VitalZeroDelay01;        tipd_D7           : VitalDelayType01  := VitalZeroDelay01;        tipd_D8           : VitalDelayType01  := VitalZeroDelay01;        tipd_D9           : VitalDelayType01  := VitalZeroDelay01;        tipd_D10          : VitalDelayType01  := VitalZeroDelay01;        tipd_D11          : VitalDelayType01  := VitalZeroDelay01;        tipd_D12          : VitalDelayType01  := VitalZeroDelay01;        tipd_D13          : VitalDelayType01  := VitalZeroDelay01;        tipd_D14          : VitalDelayType01  := VitalZeroDelay01;        tipd_D15          : VitalDelayType01  := VitalZeroDelay01;        tipd_D16          : VitalDelayType01  := VitalZeroDelay01;        tipd_D17          : VitalDelayType01  := VitalZeroDelay01;        tipd_D18          : VitalDelayType01  := VitalZeroDelay01;        tipd_D19          : VitalDelayType01  := VitalZeroDelay01;        tipd_D20          : VitalDelayType01  := VitalZeroDelay01;        tipd_D21          : VitalDelayType01  := VitalZeroDelay01;        tipd_D22          : VitalDelayType01  := VitalZeroDelay01;        tipd_D23          : VitalDelayType01  := VitalZeroDelay01;        tipd_D24          : VitalDelayType01  := VitalZeroDelay01;        tipd_D25          : VitalDelayType01  := VitalZeroDelay01;        tipd_D26          : VitalDelayType01  := VitalZeroDelay01;        tipd_D27          : VitalDelayType01  := VitalZeroDelay01;        tipd_D28          : VitalDelayType01  := VitalZeroDelay01;        tipd_D29          : VitalDelayType01  := VitalZeroDelay01;        tipd_D30          : VitalDelayType01  := VitalZeroDelay01;        tipd_D31          : VitalDelayType01  := VitalZeroDelay01;        tipd_D32          : VitalDelayType01  := VitalZeroDelay01;        tipd_D33          : VitalDelayType01  := VitalZeroDelay01;        tipd_D34          : VitalDelayType01  := VitalZeroDelay01;        tipd_D35          : VitalDelayType01  := VitalZeroDelay01;        tipd_ASYRNeg      : VitalDelayType01  := VitalZeroDelay01;        tipd_ASYWNeg      : VitalDelayType01  := VitalZeroDelay01;        tipd_FSEL0        : VitalDelayType01  := VitalZeroDelay01;        tipd_FSEL1        : VitalDelayType01  := VitalZeroDelay01;        tipd_FWFT         : VitalDelayType01  := VitalZeroDelay01;        tipd_MARK         : VitalDelayType01  := VitalZeroDelay01;        tipd_LDNeg        : VitalDelayType01  := VitalZeroDelay01;        tipd_OENeg        : VitalDelayType01  := VitalZeroDelay01;        tipd_MRSNeg       : VitalDelayType01  := VitalZeroDelay01;        tipd_PFM          : VitalDelayType01  := VitalZeroDelay01;        tipd_PRSNeg       : VitalDelayType01  := VitalZeroDelay01;        tipd_RCLK         : VitalDelayType01  := VitalZeroDelay01;        tipd_RENNeg       : VitalDelayType01  := VitalZeroDelay01;        tipd_RCSNeg       : VitalDelayType01  := VitalZeroDelay01;        tipd_RTNeg        : VitalDelayType01  := VitalZeroDelay01;        tipd_SENNeg       : VitalDelayType01  := VitalZeroDelay01;        tipd_SCLK         : VitalDelayType01  := VitalZeroDelay01;        tipd_WCLK         : VitalDelayType01  := VitalZeroDelay01;        tipd_WENNeg       : VitalDelayType01  := VitalZeroDelay01;        tipd_WCSNeg       : VitalDelayType01  := VitalZeroDelay01;        -- tpd delays:        -- tA        tpd_RCLK_Q0_SYN_EQ_1      : VitalDelayType01Z := UnitDelay01Z;        tpd_RCLK_Q0_ASYN_EQ_1     : VitalDelayType01Z := UnitDelay01Z;        -- tOLZ,tOHZ,tOE        tpd_OENeg_Q0_SYN_EQ_1     : VitalDelayType01Z := UnitDelay01Z;        tpd_OENeg_Q0_ASYN_EQ_1    : VitalDelayType01Z := UnitDelay01Z;        -- tRSF        tpd_MRSNeg_EF1Neg  : VitalDelayType01 := UnitDelay01;        tpd_MRSNeg_FF1Neg  : VitalDelayType01 := UnitDelay01;        tpd_MRSNeg_PAE1Neg : VitalDelayType01 := UnitDelay01;        tpd_MRSNeg_PAF1Neg : VitalDelayType01 := UnitDelay01;        tpd_MRSNeg_Q0     : VitalDelayType01Z := UnitDelay01Z;        tpd_PRSNeg_EF1Neg  : VitalDelayType01 := UnitDelay01;        tpd_PRSNeg_FF1Neg  : VitalDelayType01 := UnitDelay01;        tpd_PRSNeg_PAE1Neg : VitalDelayType01 := UnitDelay01;        tpd_PRSNeg_PAF1Neg : VitalDelayType01 := UnitDelay01;        tpd_PRSNeg_Q0     : VitalDelayType01Z := UnitDelay01Z;        -- tWFF,tREF,tPAFS,tPAES,tPAFA,tPAEA,tHF        tpd_WCLK_FF1Neg_SYN_EQ_1    : VitalDelayType01 := UnitDelay01;        tpd_WCLK_FF1Neg_ASYN_EQ_1   : VitalDelayType01 := UnitDelay01;        tpd_RCLK_FF1Neg             : VitalDelayType01 := UnitDelay01;        tpd_RCLK_EF1Neg_SYN_EQ_1    : VitalDelayType01 := UnitDelay01;        tpd_RCLK_EF1Neg_ASYN_EQ_1   : VitalDelayType01 := UnitDelay01;        tpd_WCLK_EF1Neg             : VitalDelayType01 := UnitDelay01;        tpd_RCLK_EF1Neg             : VitalDelayType01 := UnitDelay01;        tpd_WCLK_PAF1Neg_ASYN_EQ_1  : VitalDelayType01 := UnitDelay01;        tpd_WCLK_PAF1Neg_SYN_EQ_1   : VitalDelayType01 := UnitDelay01;        tpd_RCLK_PAF1Neg            : VitalDelayType01 := UnitDelay01;        tpd_RCLK_PAE1Neg_ASYN_EQ_1  : VitalDelayType01 := UnitDelay01;        tpd_RCLK_PAE1Neg_SYN_EQ_1   : VitalDelayType01 := UnitDelay01;        tpd_WCLK_PAE1Neg            : VitalDelayType01 := UnitDelay01;        -- tsetup values: setup times        -- tDS        tsetup_D0_WCLK       : VitalDelayType := UnitDelay;        tsetup_FWFT_SCLK     : VitalDelayType := UnitDelay;        -- tENS,tLDS,tWCSS        tsetup_WENNeg_WCLK  : VitalDelayType := UnitDelay;        tsetup_LDNeg_WCLK   : VitalDelayType := UnitDelay;        tsetup_WCSNeg_WCLK  : VitalDelayType := UnitDelay;        tsetup_LDNeg_RCLK   : VitalDelayType := UnitDelay;        tsetup_RENNeg_RCLK  : VitalDelayType := UnitDelay;        tsetup_WENNeg_RCLK  : VitalDelayType := UnitDelay;        tsetup_RTNeg_RCLK   : VitalDelayType := UnitDelay;        tsetup_RCSNeg_RCLK  : VitalDelayType := UnitDelay;        tsetup_MARK_RCLK    : VitalDelayType := UnitDelay;        tsetup_LDNeg_SCLK   : VitalDelayType := UnitDelay;        tsetup_SENNeg_SCLK  : VitalDelayType := UnitDelay;        -- tRSS        tsetup_RENNeg_MRSNeg  : VitalDelayType := UnitDelay;        tsetup_WENNeg_MRSNeg  : VitalDelayType := UnitDelay;        tsetup_FWFT_MRSNeg    : VitalDelayType := UnitDelay;        tsetup_LDNeg_MRSNeg   : VitalDelayType := UnitDelay;        tsetup_FSEL0_MRSNeg   : VitalDelayType := UnitDelay;        tsetup_FSEL1_MRSNeg   : VitalDelayType := UnitDelay;        tsetup_PFM_MRSNeg     : VitalDelayType := UnitDelay;        tsetup_RTNeg_MRSNeg   : VitalDelayType := UnitDelay;        tsetup_SENNeg_MRSNeg  : VitalDelayType := UnitDelay;        tsetup_RENNeg_PRSNeg  : VitalDelayType := UnitDelay;        tsetup_WENNeg_PRSNeg  : VitalDelayType := UnitDelay;        tsetup_RTNeg_PRSNeg   : VitalDelayType := UnitDelay;        tsetup_SENNeg_PRSNeg  : VitalDelayType := UnitDelay;        -- thold values: hold times        -- tDH        thold_D0_WCLK      : VitalDelayType := UnitDelay;        thold_FWFT_SCLK    : VitalDelayType := UnitDelay;        -- tENH,tLDH,tWCSH        thold_WENNeg_WCLK  : VitalDelayType := UnitDelay;        thold_LDNeg_WCLK   : VitalDelayType := UnitDelay;        thold_WCSNeg_WCLK  : VitalDelayType := UnitDelay;        thold_LDNeg_RCLK   : VitalDelayType := UnitDelay;        thold_RENNeg_RCLK  : VitalDelayType := UnitDelay;        thold_RTNeg_RCLK   : VitalDelayType := UnitDelay;        thold_RCSNeg_RCLK  : VitalDelayType := UnitDelay;        thold_MARK_RCLK    : VitalDelayType := UnitDelay;        thold_LDNeg_SCLK   : VitalDelayType := UnitDelay;        thold_SENNeg_SCLK  : VitalDelayType := UnitDelay;        -- tRSR        thold_RENNeg_MRSNeg : VitalDelayType := UnitDelay;        thold_WENNeg_MRSNeg : VitalDelayType := UnitDelay;        thold_FWFT_MRSNeg   : VitalDelayType := UnitDelay;        thold_LDNeg_MRSNeg  : VitalDelayType := UnitDelay;        thold_RENNeg_PRSNeg : VitalDelayType := UnitDelay;        thold_WENNeg_PRSNeg : VitalDelayType := UnitDelay;        -- tpw values: pulse widths        -- tCLKL, tCLKH        tpw_WCLK_SYN_EQ_1_negedge   : VitalDelayType := UnitDelay;        tpw_WCLK_ASYN_EQ_1_negedge  : VitalDelayType := UnitDelay;        tpw_WCLK_SYN_EQ_1_posedge   : VitalDelayType := UnitDelay;        tpw_WCLK_ASYN_EQ_1_posedge  : VitalDelayType := UnitDelay;        tpw_RCLK_SYN_EQ_1_negedge   : VitalDelayType := UnitDelay;        tpw_RCLK_ASYN_EQ_1_negedge  : VitalDelayType := UnitDelay;        tpw_RCLK_SYN_EQ_1_posedge   : VitalDelayType := UnitDelay;        tpw_RCLK_ASYN_EQ_1_posedge  : VitalDelayType := UnitDelay;        tpw_SCLK_posedge            : VitalDelayType := UnitDelay;        tpw_SCLK_negedge            : VitalDelayType := UnitDelay;        -- tPW        tpw_MRSNeg_negedge  : VitalDelayType := UnitDelay;        tpw_PRSNeg_negedge  : VitalDelayType := UnitDelay;        -- tperiod values        -- tCLK        tperiod_WCLK_SYN_EQ_1_posedge  : VitalDelayType := UnitDelay;        tperiod_WCLK_ASYN_EQ_1_posedge : VitalDelayType := UnitDelay;        tperiod_RCLK_SYN_EQ_1_posedge  : VitalDelayType := UnitDelay;        tperiod_RCLK_ASYN_EQ_1_posedge : VitalDelayType := UnitDelay;        tperiod_SCLK_posedge           : VitalDelayType := UnitDelay;        -- tSKEW1 (skew time)        tdevice_SKEW1  : VitalDelayType := UnitDelay;        -- tSKEW2 (skew time)        tdevice_SKEW2  : VitalDelayType := UnitDelay;        -- tRPE (skew time)        tdevice_RPE    : VitalDelayType := UnitDelay;        -- generic control parameters        InstancePath    : STRING  := DefaultInstancePath;        TimingChecksOn  : BOOLEAN := DefaultTimingChecks;        MsgOn           : BOOLEAN := DefaultMsgOn;        XOn             : BOOLEAN := DefaultXOn;        TimingModel     : STRING  := DefaultTimingModel);    PORT (        D0         : IN  std_ulogic := 'U';  --        D1         : IN  std_ulogic := 'U';  --        D2         : IN  std_ulogic := 'U';  --        D3         : IN  std_ulogic := 'U';  --        D4         : IN  std_ulogic := 'U';  --  Data Input Bus        D5         : IN  std_ulogic := 'U';  --        D6         : IN  std_ulogic := 'U';  --        D7         : IN  std_ulogic := 'U';  --        D8         : IN  std_ulogic := 'U';  --        D9         : IN  std_ulogic := 'U';  --        D10        : IN  std_ulogic := 'U';  --        D11        : IN  std_ulogic := 'U';  --        D12        : IN  std_ulogic := 'U';  --        D13        : IN  std_ulogic := 'U';  --        D14        : IN  std_ulogic := 'U';  --  Data Input Bus        D15        : IN  std_ulogic := 'U';  --        D16        : IN  std_ulogic := 'U';  --        D17        : IN  std_ulogic := 'U';  --        D18        : IN  std_ulogic := 'U';  --        D19        : IN  std_ulogic := 'U';  --        D20        : IN  std_ulogic := 'U';  --        D21        : IN  std_ulogic := 'U';  --        D22        : IN  std_ulogic := 'U';  --        D23        : IN  std_ulogic := 'U';  --        D24        : IN  std_ulogic := 'U';  --  Data Input Bus        D25        : IN  std_ulogic := 'U';  --        D26        : IN  std_ulogic := 'U';  --        D27        : IN  std_ulogic := 'U';  --        D28        : IN  std_ulogic := 'U';  --        D29        : IN  std_ulogic := 'U';  --        D30        : IN  std_ulogic := 'U';  --        D31        : IN  std_ulogic := 'U';  --        D32        : IN  std_ulogic := 'U';  --        D33        : IN  std_ulogic := 'U';  --        D34        : IN  std_ulogic := 'U';  --  Data Input Bus        D35        : IN  std_ulogic := 'U';  --        ASYRNeg    : IN  std_ulogic := 'U';  --  Asynchronous Read Port        ASYWNeg    : IN  std_ulogic := 'U';  --  Asynchronous Write Port        FSEL0      : IN  std_ulogic := 'U';  --  Flag Select Bit 0        FSEL1      : IN  std_ulogic := 'U';  --  Flag Select Bit 1        FWFT       : IN  std_ulogic := 'U';  --  First Word FallThrough        LDNeg      : IN  std_ulogic := 'U';  --  Load        MARK       : IN  std_ulogic := 'U';  --  Mark for Retransmit        OENeg      : IN  std_ulogic := 'U';  --  Output Enable        MRSNeg     : IN  std_ulogic := 'U';  --  Master Reset        PFM        : IN  std_ulogic := 'U';  --  Programmable Flag Mode        PRSNeg     : IN  std_ulogic := 'U';  --  Partial Reset        RCLK       : IN  std_ulogic := 'U';  --  Read Clock        RENNeg     : IN  std_ulogic := 'U';  --  Read Enable        RCSNeg     : IN  std_ulogic := 'U';  --  Read Chip Select        RTNeg      : IN  std_ulogic := 'U';  --  Retrasmint        SENNeg     : IN  std_ulogic := 'U';  --  Serial Enable        SCLK       : IN  std_ulogic := 'U';  --  Serial Clock        WCLK       : IN  std_ulogic := 'U';  --  Write Clock        WENNeg     : IN  std_ulogic := 'U';  --  Write Enable        WCSNeg     : IN  std_ulogic := 'U';  --  Write Chip Select
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