idt723644.vhd

VHDL的ram和fifo model code 包含众多的厂家

     
    ----------------------------------------------------------------------------
    -- Internal Signals for Full /Empty  FLAGS implementation according
    -- to IDT Verilog gate-level model simulation 
    
    SIGNAL STATE1A,STATE1B,STATE2A,STATE2B:STD_LOGIC;
    SIGNAL F1ORA,F2ORA,F3ORA,WrORA,WrFORA,BYPA :STD_LOGIC;
    SIGNAL F1ORB,F2ORB,F3ORB,WrORB,WrFORB,BYPB:STD_LOGIC;
    SIGNAL F1IRA,F2IRA,WrIRA,WrFIRA :STD_LOGIC;
    SIGNAL F1IRB,F2IRB,WrIRB,WrFIRB :STD_LOGIC;
    SIGNAL B0C1ORA,B0C1ORB: NATURAL;
    SIGNAL B0C1IRA,B0C1IRB: NATURAL;
    SIGNAL OPTEO :STD_LOGIC;
    
    SIGNAL En_ORB, En2_ORB : STD_LOGIC;
    SIGNAL Counter1_ORB, Counter2_ORB : STD_LOGIC;
    SIGNAL EFlGen_B, EF1l_B, EF2l_B, ORB_B2 : STD_LOGIC;
    SIGNAL EF2l_B_add : STD_LOGIC;
    SIGNAL AFTEn_AE_B, Eql_ORB, Eq_ORB : STD_LOGIC;
    SIGNAL BMAft_ORB, BMAft_Reg3 : STD_LOGIC;
    SIGNAL RDP_1, ReadPtr1_l_int    : Natural RANGE 0 TO FIFOSize-1;
    SIGNAL ReadPtr1_l_int_add : std_logic; 
    
    CONSTANT FIFOPOWER : POSITIVE := OffsetSize;  
    
    ----------------------------------------------------------------------------
    -- Internal Signals for AFA/AEA/AFB/AEB FLAGS implementation according
    -- to IDT Verilog gate-level model simulation 
    
    SIGNAL IRHdl2 : STD_LOGIC;
    SIGNAL UniEnl : STD_LOGIC := '1';
    SIGNAL BEFWFTl : STD_LOGIC;
    
    SIGNAL MRSTl1, PRSTl1 : STD_LOGIC;
    SIGNAL MRSTl2, PRSTl2 : STD_LOGIC;
    
    SIGNAL Rd_Ptr1, Wr_Ptr1, Rd_Ptr2, Wr_Ptr2 :
                               STD_LOGIC_VECTOR (FIFOPOWER -1 DOWNTO 0);
    
    SIGNAL AFlGen_A, AF1l_A, AF2l_A, AFlA : STD_LOGIC; 
    SIGNAL RcvEn_AF_A, BCmpEn_AF_A : STD_LOGIC;
    
    SIGNAL AFlGen_B, AF1l_B, AF2l_B, AFlB : STD_LOGIC; 
    SIGNAL RcvEn_AF_B, BCmpEn_AF_B : STD_LOGIC;
    SIGNAL En_IRB, En2_IRB : STD_LOGIC;
    SIGNAL Counter1_IRB, Counter2_IRB : STD_LOGIC;
   
    SIGNAL AElGen_A, AE1l_A, AE2l_A, AElA : STD_LOGIC; 
    SIGNAL RcvEn_AE_A, BCmpEn_AE_A : STD_LOGIC;
    SIGNAL EF2l_A, ORA_B2 : STD_LOGIC;
    SIGNAL ORA_Next : STD_LOGIC;
    
    SIGNAL AElGen_B, AE1l_B, AE2l_B, AElB : STD_LOGIC; 
    SIGNAL RcvEn_AE_B, BCmpEn_AE_B : STD_LOGIC;
    
    SIGNAL AF_A, AE_A, AF_B, AE_B : STD_LOGIC_VECTOR (FIFOPOWER - 1 DOWNTO 0);
  
  BEGIN -- VitalBehavior block
     
--------------------------------------------------------------------------------
-- Timing Check Section                                                         
--------------------------------------------------------------------------------
     TimingChecks: PROCESS ( A_ipd, B_ipd, BEFWFT, BM, CLKA, CLKB, CSANeg,
       CSBNeg, ENA, ENB, FS0SD, FS1SEN, MBA, MBB, MRS1Neg, MRS2Neg, PRS1Neg,
       PRS2Neg, SIZE, SPMNeg, WRA, WRB)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;

    -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_B0_CLKB       : X01 := '0';
      VARIABLE TD_B0_CLKB          : VitalTimingDataType;

      VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENA_CLKA      : X01 := '0';
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_MBA_CLKA      : X01 := '0';
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_CSBNeg_CLKB   : X01 := '0';
      VARIABLE TD_CSBNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_WRB_CLKB      : X01 := '0';
      VARIABLE TD_WRB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_ENB_CLKB      : X01 := '0';
      VARIABLE TD_ENB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_MBB_CLKB      : X01 := '0';
      VARIABLE TD_MBB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_MRS1Neg_CLKA  : X01 := '0';
      VARIABLE TD_MRS1Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_MRS1Neg_CLKB  : X01 := '0';
      VARIABLE TD_MRS1Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_MRS2Neg_CLKA  : X01 := '0';
      VARIABLE TD_MRS2Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_MRS2Neg_CLKB  : X01 := '0';
      VARIABLE TD_MRS2Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_PRS1Neg_CLKA  : X01 := '0';
      VARIABLE TD_PRS1Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PRS1Neg_CLKB  : X01 := '0';
      VARIABLE TD_PRS1Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_PRS2Neg_CLKA  : X01 := '0';
      VARIABLE TD_PRS2Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PRS2Neg_CLKB  : X01 := '0';
      VARIABLE TD_PRS2Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_MRS1Neg : X01 := '0';
      VARIABLE TD_FS0SD_MRS1Neg    : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_MRS1Neg: X01 := '0';
      VARIABLE TD_FS1SEN_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_MRS2Neg : X01 := '0';
      VARIABLE TD_FS0SD_MRS2Neg    : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_MRS2Neg: X01 := '0';
      VARIABLE TD_FS1SEN_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_MRS1Neg: X01 := '0';
      VARIABLE TD_BEFWFT_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_MRS2Neg: X01 := '0';
      VARIABLE TD_BEFWFT_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_SPMNeg_MRS1Neg: X01 := '0';
      VARIABLE TD_SPMNeg_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_SPMNeg_MRS2Neg: X01 := '0';
      VARIABLE TD_SPMNeg_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_CLKA    : X01 := '0';
      VARIABLE TD_FS0SD_CLKA       : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_CLKA   : X01 := '0';
      VARIABLE TD_FS1SEN_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_CLKA   : X01 := '0';
      VARIABLE TD_BEFWFT_CLKA      : VitalTimingDataType;

    -- Violation variable (used to OR all individual violation variables)

      VARIABLE Violation           : X01 := '0';
    
BEGIN

--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------
 IF  (TimingChecksOn) THEN

      -- CLKA period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKA,
          TestSignalName  => "CLKA",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKA);

      -- CLKB period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKB,
          TestSignalName  => "CLKB",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKB);

      -- A/CLKA setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => A_ipd,
          TestSignalName  => "A",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSANeg = '0') AND (WRA = '1') AND (ENA = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_A0_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_A0_CLKA);

   -- B/CLKB setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => B_ipd,
          TestSignalName  => "B",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSBNeg = '0') AND (WRB = '0') AND (ENB = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_B0_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => TViol_B0_CLKB);

      -- CSANeg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSANeg,
          TestSignalName  => "CSANeg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupLow        => tENS,
          SetupHigh       => tENS,
          HoldLow         => tENH,
          HoldHigh        => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSANeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSANeg_CLKA);

      -- WRA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRA,
          TestSignalName  => "WRA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRA_CLKA);

      -- ENA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENA,
          TestSignalName  => "ENA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENA_CLKA);

      -- MBA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBA,
          TestSignalName  => "MBA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBA_CLKA);

      -- CSBNeg/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSBNeg,
          TestSignalName  => "CSBNeg",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupLow        => tENS,
          SetupHigh       => tENS,
          HoldLow         => tENH,
          HoldHigh        => tENH,