idt72132.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
--  File Name: idt72132.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    01 Jan 24   Initial release
--    V1.1    R. Munden    01 Sep 15   Fixed bug that caused full flag to
--                                     go low one word early sometimes
--    V1.2    B. Bizic     01 Sep 25   Corrected wr_inhibit
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    FIFO
--  Technology: CMOS
--  Part:       IDT72132
-- 
--  Description: Serial to Parallel FIFO 2048 x 9
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt72132 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_SI                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_SICP                : VitalDelayType01 := VitalZeroDelay01;
        tipd_NWNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_SIX                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_XINeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_FLNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_RNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_SICP_D7              : VitalDelayType01 := UnitDelay01;
        tpd_SICP_FFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_SICP_EFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_SICP_XONeg           : VitalDelayType01 := UnitDelay01; --HF
        tpd_SICP_AEFNeg          : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_D7             : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_FFNeg          : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_EFNeg          : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_XONeg          : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_AEFNeg         : VitalDelayType01 := UnitDelay01;
        tpd_RNeg_Q0              : VitalDelayType01Z := UnitDelay01Z;
        tpd_RNeg_FFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_RNeg_EFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_RNeg_XONeg           : VitalDelayType01 := UnitDelay01; --XO
        tpd_RNeg_AEFNeg          : VitalDelayType01 := UnitDelay01;
        tpd_OENeg_Q0             : VitalDelayType01Z := UnitDelay01Z;
        -- tsetup values: setup times
        tsetup_SI_SICP           : VitalDelayType := UnitDelay;
        tsetup_SIX_SICP          : VitalDelayType := UnitDelay;
        tsetup_SICP_RSNeg        : VitalDelayType := UnitDelay;
        tsetup_SICP_FLNeg        : VitalDelayType := UnitDelay;
        tsetup_RNeg_XINeg        : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_SI_SICP            : VitalDelayType := UnitDelay;
        thold_RNeg_EFNeg         : VitalDelayType := UnitDelay;
        thold_SICP_RSNeg         : VitalDelayType := UnitDelay;
        thold_SICP_FLNeg         : VitalDelayType := UnitDelay;
        -- trecovery values: release times
        trecovery_SICP_FFNeg   : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_SICP_negedge         : VitalDelayType := UnitDelay;
        tpw_RNeg_negedge         : VitalDelayType := UnitDelay;
        tpw_RNeg_posedge         : VitalDelayType := UnitDelay;
        tpw_RSNeg_negedge        : VitalDelayType := UnitDelay;
        tpw_FLNeg_negedge        : VitalDelayType := UnitDelay;
        tpw_XINeg_negedge        : VitalDelayType := UnitDelay;
        tpw_XINeg_posedge        : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_RNeg_negedge     : VitalDelayType := UnitDelay;
        tperiod_SICP_negedge     : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        Q8              : OUT   std_ulogic := 'U';
        Q7              : OUT   std_ulogic := 'U';
        Q6              : OUT   std_ulogic := 'U';
        Q5              : OUT   std_ulogic := 'U';
        Q4              : OUT   std_ulogic := 'U';
        Q3              : OUT   std_ulogic := 'U';
        Q2              : OUT   std_ulogic := 'U';
        Q1              : OUT   std_ulogic := 'U';
        Q0              : OUT   std_ulogic := 'U';
        D8              : OUT   std_ulogic := 'U';
        D7              : OUT   std_ulogic := 'U';
        FFNeg           : OUT   std_ulogic := 'U';
        EFNeg           : OUT   std_ulogic := 'U';
        XONeg           : OUT   std_ulogic := 'U';
        AEFNeg          : OUT   std_ulogic := 'U';
        SI              : IN    std_ulogic := 'U';
        SICP            : IN    std_ulogic := 'U';
        NWNeg           : IN    std_ulogic := 'U';
        SIX             : IN    std_ulogic := 'U';
        XINeg           : IN    std_ulogic := 'U';
        FLNeg           : IN    std_ulogic := 'U';
        RSNeg           : IN    std_ulogic := 'U';
        RNeg            : IN    std_ulogic := 'U';
        OENeg           : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt72132 : ENTITY IS TRUE;
END idt72132;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt72132 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE;

    CONSTANT partID         : STRING := "idt72132";
    CONSTANT MaxData        : NATURAL := 511;
    CONSTANT TotalLOC       : NATURAL := 2047;
    CONSTANT Half           : NATURAL := 1024;
    CONSTANT Ael            : NATURAL := 256;
    CONSTANT Aeh            : NATURAL := 1792;
    CONSTANT DataWidth      : NATURAL := 9;
    CONSTANT HiDbit         : NATURAL := 8;

    SIGNAL SI_ipd              : std_ulogic := 'U';
    SIGNAL SICP_ipd            : std_ulogic := 'U';
    SIGNAL NWNeg_ipd           : std_ulogic := 'U';
    SIGNAL SIX_ipd             : std_ulogic := 'U';
    SIGNAL XINeg_ipd           : std_ulogic := 'U';
    SIGNAL FLNeg_ipd           : std_ulogic := 'U';
    SIGNAL RSNeg_ipd           : std_ulogic := 'U';
    SIGNAL RNeg_ipd            : std_ulogic := 'U';
    SIGNAL OENeg_ipd           : std_ulogic := 'U';
    SIGNAL EFNeg_int           : std_ulogic := 'U';
    SIGNAL FFNeg_int           : std_ulogic := 'U';
    SIGNAL Q_zd      : std_logic_vector(HiDbit downto 0) := (others => 'Z');
    SIGNAL Qout      : std_logic_vector(HiDbit downto 0) := (others => 'Z');

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_16 : VitalWireDelay (SI_ipd, SI, tipd_SI);
        w_17 : VitalWireDelay (SICP_ipd, SICP, tipd_SICP);
        w_18 : VitalWireDelay (NWNeg_ipd, NWNeg, tipd_NWNeg);
        w_19 : VitalWireDelay (SIX_ipd, SIX, tipd_SIX);
        w_20 : VitalWireDelay (XINeg_ipd, XINeg, tipd_XINeg);
        w_21 : VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg);
        w_22 : VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);
        w_23 : VitalWireDelay (RNeg_ipd, RNeg, tipd_RNeg);
        w_24 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);

    END BLOCK;

    EFNeg <= EFNeg_int;
    FFNeg <= FFNeg_int;
    Q8 <= Qout(8);
    Q7 <= Qout(7);
    Q6 <= Qout(6);
    Q5 <= Qout(5);
    Q4 <= Qout(4);
    Q3 <= Qout(3);
    Q2 <= Qout(2);
    Q1 <= Qout(1);
    Q0 <= Qout(0);

    ----------------------------------------------------------------------------
    -- Behavior Process
    ----------------------------------------------------------------------------
    VITALBehaviour : PROCESS (SI_ipd, SICP_ipd, NWNeg_ipd, SIX_ipd, XINeg_ipd,
                              FLNeg_ipd, RSNeg_ipd, RNeg_ipd, OENeg_ipd, 
                              EFNeg_int)

        -- Timing Check Variables
        VARIABLE Tviol_SI_SICP   : X01 := '0';
        VARIABLE TD_SI_SICP      : VitalTimingDataType;

        VARIABLE Tviol_SIX_SICP  : X01 := '0';
        VARIABLE TD_SIX_SICP     : VitalTimingDataType;

        VARIABLE Tviol_RNeg_EF   : X01 := '0';
        VARIABLE TD_RNeg_EF      : VitalTimingDataType;

        VARIABLE Tviol_SICP_RSNeg : X01 := '0';
        VARIABLE TD_SICP_RSNeg    : VitalTimingDataType;

        VARIABLE Tviol_RNeg_RSNeg : X01 := '0';
        VARIABLE TD_RNeg_RSNeg    : VitalTimingDataType;

        VARIABLE Tviol_SICP_FLNeg : X01 := '0';
        VARIABLE TD_SICP_FLNeg    : VitalTimingDataType;

        VARIABLE Tviol_XINeg_SICP : X01 := '0';
        VARIABLE TD_XINeg_SICP    : VitalTimingDataType;

        VARIABLE Tviol_XINeg_RNeg : X01 := '0';
        VARIABLE TD_XINeg_RNeg    : VitalTimingDataType;

        VARIABLE Rviol_SICP_FFNeg   : X01 := '0';
        VARIABLE TD_SICP_FFNeg      : VitalTimingDataType;

        VARIABLE Pviol_RNeg      : X01 := '0';
        VARIABLE PD_RNeg         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_SICP      : X01 := '0';
        VARIABLE PD_SICP         : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_RSNeg     : X01 := '0';
        VARIABLE PD_RSNeg        : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_FLNeg     : X01 := '0';
        VARIABLE PD_FLNeg        : VitalPeriodDataType := VitalPeriodDataInit;

        VARIABLE Pviol_XINeg     : X01 := '0';
        VARIABLE PD_XINeg        : VitalPeriodDataType := VitalPeriodDataInit;

        -- Memory array declaration
        TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                         RANGE  -2 TO MaxData;

        -- Functionality Results Variables
        VARIABLE Violation  : X01 := '0';

        TYPE mode_type IS (unk, single, first_exp, other_exp);
        TYPE stat_type IS (inact, act);

        VARIABLE mode            : mode_type;
        VARIABLE rd_stat         : stat_type;
        VARIABLE wr_stat         : stat_type;
        VARIABLE FFNeg_zd        : std_ulogic;
        VARIABLE EFNeg_zd        : std_ulogic;
        VARIABLE XONeg_zd        : std_ulogic;
        VARIABLE AEFNeg_zd       : std_ulogic;
        VARIABLE D8_zd           : std_ulogic;
        VARIABLE D7_zd           : std_ulogic;

        VARIABLE reset_done      : boolean := false;
        VARIABLE wr_inhibit      : boolean := false;
        VARIABLE RDPoint    : NATURAL RANGE 0 TO TotalLoc := 0;
        VARIABLE WRPoint    : NATURAL RANGE 0 TO TotalLoc := 0;
        VARIABLE Count      : NATURAL RANGE 0 TO TotalLoc := 0;
        VARIABLE sicnt      : NATURAL RANGE 0 TO HiDbit + 1 := 0;
        VARIABLE MemData    : MemStore;
        VARIABLE DataDrive  : std_logic_vector(HiDbit DOWNTO 0)
                                  := (OTHERS => 'Z');
        VARIABLE in_reg     : std_logic_vector(HiDbit DOWNTO 0)
                                  := (OTHERS => 'Z');

        -- Output Glitch Detection Variables
        VARIABLE FF_GlitchData   : VitalGlitchDataType;
        VARIABLE EF_GlitchData   : VitalGlitchDataType;
        VARIABLE XO_GlitchData   : VitalGlitchDataType;
        VARIABLE AEF_GlitchData  : VitalGlitchDataType;
        VARIABLE D8_GlitchData   : VitalGlitchDataType;
        VARIABLE D7_GlitchData   : VitalGlitchDataType;

        -- No Weak Values Variables
        VARIABLE NWNeg_nwv       : UX01 := 'U';
        VARIABLE RSNeg_nwv       : UX01 := 'U';
        VARIABLE XINeg_nwv       : UX01 := 'U';
        VARIABLE FLNeg_nwv       : UX01 := 'U';
        VARIABLE RNeg_nwv        : UX01 := 'U';
        VARIABLE OENeg_nwv       : UX01 := 'U';
        VARIABLE SIX_nwv         : UX01 := 'U';
        VARIABLE SI_nwv          : UX01 := 'U';

    BEGIN
        NWNeg_nwv      := To_UX01 (s => NWNeg_ipd);
        RSNeg_nwv      := To_UX01 (s => RSNeg_ipd);