idt723624.vhd

VHDL的ram和fifo model code 包含众多的厂家

     SIGNAL ReadPtr1int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL ReadPtr2int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr1int   : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr2int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- FIFO Offset for Almoust Empty/Full Flags
     
     SIGNAL X1int, X2int,
            Y1int, Y2int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- Mail Registers
     
     SIGNAL Mail1int,
            Mail2int       : MailWord := (OTHERS => 'X');
            
     -- Flags for Standart and FWFT mode
     
     SIGNAL EFANegint, EFBNegint, FFANegint, FFBNegint,	-- standard mode 
     	    ORAint, ORBint				-- FWFT mode
     	    : std_ulogic;    

     -- Flags Flip-flop first stage (each flag is synchonized 
     -- to its Port Clock through two flip-flop stages)
     
     SIGNAL EFA1int, EFB1int, FFA1int, FFB1int, 
            AEA1int, AEB1int, AFA1int, AFB1int : std_ulogic;
      
     ---------- Input Registers Controlling Signals ------------      
     -- Flags "Input Register is loaded" - in this 
     -- model they will be loaded to FIFOMemory on CLK negedge      
     SIGNAL InputReg1Readyint   : std_ulogic; 
     SIGNAL InputReg2Readyint   : std_ulogic; 
     SIGNAL InputReg2ReadyNextint   : std_ulogic; 
     
     -- Pointer for Byte/Word Access for PortB
     SIGNAL InputReg2Ptrint  : Natural RANGE 0 TO FIFOWordBytes-1;
     
     ---------- Output Registers Controlling Signals ------------      
     SIGNAL OutputReg1Readyint : std_ulogic; -- all 4-bytes have been
     				 	    -- read to Port-B 
     SIGNAL OutputReg1ReadyNextint : std_ulogic;
                                            -- all 4-bytes will be 
     				 	    -- read to Port-B next CLKB
     				 	    -- posedge
     -- Pointers for Byte/Word Access for PortB
        
     SIGNAL OutputReg1Ptrint : Natural RANGE 0 TO FIFOWordBytes-1;
     
	     						   
       -- Pointers for Byte/Word Access that will be latched on CLKB posedge
       	     						   
       SIGNAL OutputReg1PtrNextint   : Natural RANGE 0 TO FIFOWordBytes - 1;
         
     SIGNAL OutputReg2Readyint : std_ulogic; -- word have been read to Port-A
     
     SIGNAL FWFTFirst : std_ulogic; -- first word though in FWFT mode
     
     -------------------------------------------------------------------------  
     -- Master Reset 1,2 / Partial Reset 1,2
     
     SIGNAL RST1int, RST2int: std_ulogic; -- MRS1Neg AND PRS1Neg; MRS2Neg AND PRS2Neg
     
     -- Master Reset (MRS1Neg = '0' and MRS2Neg = '0') done
     
     SIGNAL MRSDoneint: std_ulogic := '0';
     
     -- "Simultaneous Master Reset"
   
     SIGNAL  MRSint: std_ulogic;
     
     -- Counters of Clocks during Master/Partion Reset is active or just after
     -- Reset
     
     SIGNAL CountCLKA1int, CountCLKA2int, CountCLKB1int, CountCLKB2int: Natural;
     
     -- MRS1Neg, MRS2Neg states on CLKA posedge 
     
     SIGNAL MRS1CLKAint, MRS2CLKAint: std_ulogic;
     
     -- Big Endian ('1') / Little Endian ('0') Mode
     
     SIGNAL BEint: std_ulogic;
     
     -- Internal Control Signals
     
     SIGNAL EnWrFIFO1int, EnRdFIFO1int, EnWrFIFO2int, EnRdFIFO2int,
     	    EnWrMail1int, EnRdMail1int, EnWrMail2int, EnRdMail2int: std_ulogic; 
     	    
     ---------------------------------------------------------------------------
     -- ALmost-Empty/Almost-Full Offsets Loading Mode
     
     SIGNAL Offs_Par_Load_Modeint : bit := '0'; -- Parallel Offsets Loading Mode
     SIGNAL Offs_Ser_Load_Modeint : bit := '0'; -- Serial Offsets Loading Mode
     
     -- Word/Bit Counter while Offset Loading
     
     SIGNAL CountLoadOffsetint: Natural; 
     
     
     ---------------------------------------------------------------------------
     -- Additional Signals
     
     SIGNAL SIZBint: std_ulogic;
     
     	         
  
  BEGIN -- VitalBehavior block
     
--------------------------------------------------------------------------------
-- Timing Check Section                                                         
--------------------------------------------------------------------------------

     TimingChecks: PROCESS ( A_ipd, B_ipd, BEFWFT, BM, CLKA, CLKB, CSANeg,
                   CSBNeg, ENA, ENB, FS0SD, FS1SEN, MBA, MBB, MRS1Neg, MRS2Neg,
                   PRS1Neg, PRS2Neg,  SIZE, SPMNeg, WRA, WRB)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;

    -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_B0_CLKB       : X01 := '0';
      VARIABLE TD_B0_CLKB          : VitalTimingDataType;

      VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENA_CLKA      : X01 := '0';
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_MBA_CLKA      : X01 := '0';
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_CSBNeg_CLKB   : X01 := '0';
      VARIABLE TD_CSBNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_WRB_CLKB      : X01 := '0';
      VARIABLE TD_WRB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_ENB_CLKB      : X01 := '0';
      VARIABLE TD_ENB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_MBB_CLKB      : X01 := '0';
      VARIABLE TD_MBB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_MRS1Neg_CLKA  : X01 := '0';
      VARIABLE TD_MRS1Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_MRS1Neg_CLKB  : X01 := '0';
      VARIABLE TD_MRS1Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_MRS2Neg_CLKA  : X01 := '0';
      VARIABLE TD_MRS2Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_MRS2Neg_CLKB  : X01 := '0';
      VARIABLE TD_MRS2Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_PRS1Neg_CLKA  : X01 := '0';
      VARIABLE TD_PRS1Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PRS1Neg_CLKB  : X01 := '0';
      VARIABLE TD_PRS1Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_PRS2Neg_CLKA  : X01 := '0';
      VARIABLE TD_PRS2Neg_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PRS2Neg_CLKB  : X01 := '0';
      VARIABLE TD_PRS2Neg_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_MRS1Neg : X01 := '0';
      VARIABLE TD_FS0SD_MRS1Neg    : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_MRS1Neg: X01 := '0';
      VARIABLE TD_FS1SEN_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_MRS2Neg : X01 := '0';
      VARIABLE TD_FS0SD_MRS2Neg    : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_MRS2Neg: X01 := '0';
      VARIABLE TD_FS1SEN_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_MRS1Neg: X01 := '0';
      VARIABLE TD_BEFWFT_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_MRS2Neg: X01 := '0';
      VARIABLE TD_BEFWFT_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_SPMNeg_MRS1Neg: X01 := '0';
      VARIABLE TD_SPMNeg_MRS1Neg   : VitalTimingDataType;

      VARIABLE Tviol_SPMNeg_MRS2Neg: X01 := '0';
      VARIABLE TD_SPMNeg_MRS2Neg   : VitalTimingDataType;

      VARIABLE Tviol_FS0SD_CLKA    : X01 := '0';
      VARIABLE TD_FS0SD_CLKA       : VitalTimingDataType;

      VARIABLE Tviol_FS1SEN_CLKA   : X01 := '0';
      VARIABLE TD_FS1SEN_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_BEFWFT_CLKA   : X01 := '0';
      VARIABLE TD_BEFWFT_CLKA      : VitalTimingDataType;

    -- Violation variable (used to OR all individual violation variables)

      VARIABLE Violation           : X01 := '0';
    
BEGIN

--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------
 IF  (TimingChecksOn)
 THEN

      -- CLKA period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKA,
          TestSignalName  => "CLKA",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKA);

      -- CLKB period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKB,
          TestSignalName  => "CLKB",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKB);

      -- A/CLKA setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => A_ipd,
          TestSignalName  => "A",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSANeg = '0') AND (WRA = '1') 
                              AND (ENA = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_A0_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_A0_CLKA);

   -- B/CLKB setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => B_ipd,
          TestSignalName  => "B",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSBNeg = '0') AND (WRB = '0') 
                              AND (ENB = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_B0_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => TViol_B0_CLKB);


      -- CSANeg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSANeg,
          TestSignalName  => "CSANeg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupLow        => tENS,
          SetupHigh       => tENS,
          HoldLow         => tENH,
          HoldHigh        => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSANeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSANeg_CLKA);

      -- WRA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRA,
          TestSignalName  => "WRA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,