idt723634.vhd

VHDL的ram和fifo model code 包含众多的厂家

    w_55: VitalWireDelay (B18_ipd,      B18,      tipd_B18     );
    w_56: VitalWireDelay (B19_ipd,      B19,      tipd_B19     );
    w_57: VitalWireDelay (B20_ipd,      B20,      tipd_B20     );
    w_58: VitalWireDelay (B21_ipd,      B21,      tipd_B21     );
    w_59: VitalWireDelay (B22_ipd,      B22,      tipd_B22     );
    w_60: VitalWireDelay (B23_ipd,      B23,      tipd_B23     );
    w_61: VitalWireDelay (B24_ipd,      B24,      tipd_B24     );
    w_62: VitalWireDelay (B25_ipd,      B25,      tipd_B25     );
    w_63: VitalWireDelay (B26_ipd,      B26,      tipd_B26     );
    w_64: VitalWireDelay (B27_ipd,      B27,      tipd_B27     );
    w_65: VitalWireDelay (B28_ipd,      B28,      tipd_B28     );
    w_66: VitalWireDelay (B29_ipd,      B29,      tipd_B29     );
    w_67: VitalWireDelay (B30_ipd,      B30,      tipd_B30     );
    w_68: VitalWireDelay (B31_ipd,      B31,      tipd_B31     );
    w_69: VitalWireDelay (B32_ipd,      B32,      tipd_B32     );
    w_70: VitalWireDelay (B33_ipd,      B33,      tipd_B33     );
    w_71: VitalWireDelay (B34_ipd,      B34,      tipd_B34     );
    w_72: VitalWireDelay (B35_ipd,      B35,      tipd_B35     );
    w_73: VitalWireDelay (BEFWFT_ipd,   BEFWFT,   tipd_BEFWFT  );
    w_74: VitalWireDelay (BM_ipd,       BM,	  tipd_BM      );
    w_75: VitalWireDelay (CLKA_ipd,     CLKA,     tipd_CLKA    );
    w_76: VitalWireDelay (CLKB_ipd,     CLKB,     tipd_CLKB    );
    w_77: VitalWireDelay (CSANeg_ipd,   CSANeg,   tipd_CSANeg  );
    w_78: VitalWireDelay (CSBNeg_ipd,   CSBNeg,   tipd_CSBNeg  );
    w_79: VitalWireDelay (ENA_ipd,      ENA,      tipd_ENA     );
    w_80: VitalWireDelay (ENB_ipd,      ENB,      tipd_ENB     );
    w_81: VitalWireDelay (FS0SD_ipd,    FS0SD,    tipd_FS0SD   );
    w_82: VitalWireDelay (FS1SEN_ipd,   FS1SEN,   tipd_FS1SEN  );
    w_83: VitalWireDelay (MBA_ipd,      MBA,      tipd_MBA     );
    w_84: VitalWireDelay (MBB_ipd,      MBB,      tipd_MBB     );
    w_85: VitalWireDelay (MRS1Neg_ipd,  MRS1Neg,  tipd_MRS1Neg );
    w_86: VitalWireDelay (MRS2Neg_ipd,  MRS2Neg,  tipd_MRS2Neg );
    w_87: VitalWireDelay (PRS1Neg_ipd,  PRS1Neg,  tipd_PRS1Neg );
    w_88: VitalWireDelay (PRS2Neg_ipd,  PRS2Neg,  tipd_PRS2Neg );
    w_89: VitalWireDelay (SIZE_ipd,     SIZE,     tipd_SIZE    );
    w_90: VitalWireDelay (SPMNeg_ipd,   SPMNeg,   tipd_SPMNeg  );
    w_91: VitalWireDelay (WRA_ipd,      WRA,      tipd_WRA     );
    w_92: VitalWireDelay (WRB_ipd,      WRB,      tipd_WRB     );

END BLOCK;

--------------------------------------------------------------------------------
-- Main Behavior Block                                                        --
--------------------------------------------------------------------------------
  VITALBehavior: BLOCK
  
  PORT (
    A_ipd    : IN std_logic_vector(35 downto 0) := (OTHERS => 'X'); 
    A        : OUT std_logic_vector(35 downto 0) := (OTHERS => 'U'); 
    AEANeg   : OUT   std_logic := 'U'; 
    AEBNeg   : OUT   std_logic := 'U'; 
    AFANeg   : OUT   std_logic := 'U'; 
    AFBNeg   : OUT   std_logic := 'U'; 
    B_ipd    : IN std_logic_vector(35 downto 0) := (OTHERS => 'X'); 
    B        : OUT std_logic_vector(35 downto 0) := (OTHERS => 'U'); 
    BEFWFT   : IN    std_logic := 'X'; 
    BM       : IN    std_logic := 'X'; 
    CLKA     : IN    std_logic := 'X'; 
    CLKB     : IN    std_logic := 'X'; 
    CSANeg   : IN    std_logic := 'X'; 
    CSBNeg   : IN    std_logic := 'X';
    EFAORA   : OUT   std_logic := 'U';
    EFBORB   : OUT   std_logic := 'U';
    ENA      : IN    std_logic := 'X';
    ENB      : IN    std_logic := 'X';
    FFAIRA   : OUT   std_logic := 'U';
    FFBIRB   : OUT   std_logic := 'U';
    FS0SD    : IN    std_logic := 'X'; 
    FS1SEN   : IN    std_logic := 'X'; 
    MBA      : IN    std_logic := 'X';
    MBB      : IN    std_logic := 'X';
    MBF1Neg  : OUT   std_logic := 'U';
    MBF2Neg  : OUT   std_logic := 'U';
    MRS1Neg  : IN    std_logic := 'X'; 
    MRS2Neg  : IN    std_logic := 'X'; 
    PRS1Neg  : IN    std_logic := 'X'; 
    PRS2Neg  : IN    std_logic := 'X';
    SIZE     : IN    std_logic := 'X'; 
    SPMNeg   : IN    std_logic := 'X';
    WRA      : IN    std_logic := 'X';  
    WRB      : IN    std_logic := 'X'  
     );
   PORT MAP (
    A_ipd(0)    => A0_ipd,
    A_ipd(1)    => A1_ipd,
    A_ipd(2)    => A2_ipd,
    A_ipd(3)    => A3_ipd,
    A_ipd(4)    => A4_ipd,
    A_ipd(5)    => A5_ipd,
    A_ipd(6)    => A6_ipd,
    A_ipd(7)    => A7_ipd,
    A_ipd(8)    => A8_ipd,
    A_ipd(9)    => A9_ipd,
    A_ipd(10)   => A10_ipd,
    A_ipd(11)   => A11_ipd,
    A_ipd(12)   => A12_ipd,
    A_ipd(13)   => A13_ipd,
    A_ipd(14)   => A14_ipd,
    A_ipd(15)   => A15_ipd,
    A_ipd(16)   => A16_ipd,
    A_ipd(17)   => A17_ipd,
    A_ipd(18)   => A18_ipd,
    A_ipd(19)   => A19_ipd,
    A_ipd(20)   => A20_ipd,
    A_ipd(21)   => A21_ipd,
    A_ipd(22)   => A22_ipd,
    A_ipd(23)   => A23_ipd,
    A_ipd(24)   => A24_ipd,
    A_ipd(25)   => A25_ipd,
    A_ipd(26)   => A26_ipd,
    A_ipd(27)   => A27_ipd,
    A_ipd(28)   => A28_ipd,
    A_ipd(29)   => A29_ipd,
    A_ipd(30)   => A30_ipd,
    A_ipd(31)   => A31_ipd,
    A_ipd(32)   => A32_ipd,
    A_ipd(33)   => A33_ipd,
    A_ipd(34)   => A34_ipd,
    A_ipd(35)   => A35_ipd,
    A(0)    	=> A0,
    A(1)    	=> A1,
    A(2)    	=> A2,
    A(3)    	=> A3,
    A(4) 	=> A4,
    A(5)  	=> A5,
    A(6)  	=> A6,
    A(7)    	=> A7,
    A(8)    	=> A8,
    A(9)    	=> A9,
    A(10)   	=> A10,
    A(11)   	=> A11,
    A(12)   	=> A12,
    A(13)   	=> A13,
    A(14)   	=> A14,
    A(15)   	=> A15,
    A(16)   	=> A16,
    A(17)   	=> A17,
    A(18)   	=> A18,
    A(19)   	=> A19,
    A(20)   	=> A20,
    A(21)   	=> A21,
    A(22)   	=> A22,
    A(23)   	=> A23,
    A(24)   	=> A24,
    A(25)   	=> A25,
    A(26)   	=> A26,
    A(27)   	=> A27,
    A(28)   	=> A28,
    A(29)   	=> A29,
    A(30)   	=> A30,
    A(31)   	=> A31,
    A(32)   	=> A32,
    A(33)   	=> A33,
    A(34)   	=> A34,
    A(35)    	=> A35,
    AEANeg  	=> AEANeg,
    AEBNeg   	=> AEBNeg,
    AFANeg   	=> AFANeg,
    AFBNeg   	=> AFBNeg,
    B_ipd(0)    => B0_ipd,
    B_ipd(1)    => B1_ipd,
    B_ipd(2)    => B2_ipd,
    B_ipd(3)    => B3_ipd,
    B_ipd(4)    => B4_ipd,
    B_ipd(5)    => B5_ipd,
    B_ipd(6)    => B6_ipd,
    B_ipd(7)    => B7_ipd,
    B_ipd(8)    => B8_ipd,
    B_ipd(9)    => B9_ipd,
    B_ipd(10)   => B10_ipd,
    B_ipd(11)   => B11_ipd,
    B_ipd(12)   => B12_ipd,
    B_ipd(13)   => B13_ipd,
    B_ipd(14)   => B14_ipd,
    B_ipd(15)   => B15_ipd,
    B_ipd(16)   => B16_ipd,
    B_ipd(17)   => B17_ipd,
    B_ipd(18)   => B18_ipd,
    B_ipd(19)   => B19_ipd,
    B_ipd(20)   => B20_ipd,
    B_ipd(21)   => B21_ipd,
    B_ipd(22)   => B22_ipd,
    B_ipd(23)   => B23_ipd,
    B_ipd(24)   => B24_ipd,
    B_ipd(25)   => B25_ipd,
    B_ipd(26)   => B26_ipd,
    B_ipd(27)   => B27_ipd,
    B_ipd(28)   => B28_ipd,
    B_ipd(29)   => B29_ipd,
    B_ipd(30)   => B30_ipd,
    B_ipd(31)   => B31_ipd,
    B_ipd(32)   => B32_ipd,
    B_ipd(33)   => B33_ipd,
    B_ipd(34)   => B34_ipd,
    B_ipd(35)   => B35_ipd,
    B(0)    	=> B0,
    B(1)    	=> B1,
    B(2)    	=> B2,
    B(3)    	=> B3,
    B(4) 	=> B4,
    B(5)  	=> B5,
    B(6)  	=> B6,
    B(7)    	=> B7,
    B(8)    	=> B8,
    B(9)    	=> B9,
    B(10)   	=> B10,
    B(11)   	=> B11,
    B(12)   	=> B12,
    B(13)   	=> B13,
    B(14)   	=> B14,
    B(15)   	=> B15,
    B(16)   	=> B16,
    B(17)   	=> B17,
    B(18)   	=> B18,
    B(19)   	=> B19,
    B(20)   	=> B20,
    B(21)   	=> B21,
    B(22)   	=> B22,
    B(23)   	=> B23,
    B(24)   	=> B24,
    B(25)   	=> B25,
    B(26)   	=> B26,
    B(27)   	=> B27,
    B(28)   	=> B28,
    B(29)   	=> B29,
    B(30)   	=> B30,
    B(31)   	=> B31,
    B(32)   	=> B32,
    B(33)   	=> B33,
    B(34)   	=> B34,
    B(35)    	=> B35,
    BEFWFT   	=> BEFWFT_ipd,
    BM   	=> BM_ipd,
    CLKA        => CLKA_ipd,
    CLKB        => CLKB_ipd,
    CSANeg      => CSANeg_ipd,
    CSBNeg      => CSBNeg_ipd,
    EFAORA   	=> EFAORA,
    EFBORB   	=> EFBORB,
    ENA         => ENA_ipd,
    ENB         => ENB_ipd,
    FFAIRA   	=> FFAIRA,
    FFBIRB   	=> FFBIRB,
    FS0SD       => FS0SD_ipd,
    FS1SEN      => FS1SEN_ipd,
    MBA         => MBA_ipd,
    MBB         => MBB_ipd,
    MBF1Neg     => MBF1Neg,
    MBF2Neg     => MBF2Neg,
    MRS1Neg     => MRS1Neg_ipd,
    MRS2Neg     => MRS2Neg_ipd,
    PRS1Neg     => PRS1Neg_ipd,
    PRS2Neg     => PRS2Neg_ipd,
    SIZE        => SIZE_ipd,
    SPMNeg      => SPMNeg_ipd,
    WRA         => WRA_ipd,
    WRB         => WRB_ipd);
    
  -- zero delayed outputs and bidirectional ports 
  -- (func. sec. uses these signals instead of =
  --  actual outputs and bidirectional ports);
  -- actual outputs are assigned in Path Delay Section
  
  SIGNAL A_zd         : std_logic_vector (35 downto 0);
  SIGNAL B_zd         : std_logic_vector (35 downto 0); 
  SIGNAL AEANeg_zd    : std_logic; 
  SIGNAL AEBNeg_zd    : std_logic;  
  SIGNAL AFANeg_zd    : std_logic;  
  SIGNAL AFBNeg_zd    : std_logic;  
  SIGNAL EFAORA_zd    : std_logic;     
  SIGNAL EFBORB_zd    : std_logic;     
  SIGNAL FFAIRA_zd    : std_logic;     
  SIGNAL FFBIRB_zd    : std_logic;     
  SIGNAL MBF1Neg_zd   : std_logic;    
  SIGNAL MBF2Neg_zd   : std_logic;   

  ------------------------------------------------------------------------------
  -- FIFO memory definitions
  ------------------------------------------------------------------------------
  -- general
  CONSTANT FIFOWordLength  :  positive := 36;
  SUBTYPE  FIFOWord    IS std_logic_vector(FIFOWordLength - 1 DOWNTO 0);
  TYPE     FIFOArray   IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord;
  
  CONSTANT MailWordLength  :  positive := 36;
  SUBTYPE  MailWord    IS std_logic_vector(MailWordLength - 1 DOWNTO 0);
  
  CONSTANT Offs_Par_Number :  positive := 4; -- Number of Words while
  					     -- Parallel Offset Loading
  CONSTANT Offs_Ser_Number :  positive := OffsetSize*4; -- Number of Bits while
  					     -- Serial Offset Loading
  
  -- special
  CONSTANT FIFOWordBytes   :  positive := 4;
  
  ------------------------------------------------------------------------------
  -- internal constants 
  ------------------------------------------------------------------------------
  
     CONSTANT SIZByte : std_logic := '1';	
     CONSTANT SIZWord : std_logic := '0';    
  
  ------------------------------------------------------------------------------
  -- internal signals 
  ------------------------------------------------------------------------------  
  -- FIFO Arrays
  
     SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
     SIGNAL FIFOMemory2int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
                                        
  -- Main Registers                                       
  
     -- Input Registers