📄 idt72264.vhd
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VitalSetupHoldCheck ( TestSignal => SENNEg, TestSignalName => "SENNeg", RefSignal => MRSNEg, RefSignalName => "MRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg); END IF; --14 RENNeg/PRSNeg setup time check (tRSS) IF RENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNEg, TestSignalName => "RENNeg", RefSignal => PRSNEg, RefSignalName => "PRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg); END IF; --15 WENNeg/PRSNeg setup time check (tRSS) IF WENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNEg, TestSignalName => "WENNeg", RefSignal => PRSNEg, RefSignalName => "PRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg); END IF; --16 RTNeg/PRSNeg setup time check (tRSS) IF RTNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNEg, TestSignalName => "RTNeg", RefSignal => PRSNEg, RefSignalName => "PRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_PRSNeg); END IF; --17 SENNeg/PRSNeg setup time check (tRSS) IF SENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNEg, TestSignalName => "SENNeg", RefSignal => PRSNEg, RefSignalName => "PRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_PRSNeg); END IF; --24 FWFTSI_MRSNeg setup time check (tFWFT) IF FWFTSI'event OR (MRSNeg'event AND MRSNeg = '0') THEN VitalSetupHoldCheck ( TestSignal => FWFTSI, TestSignalName => "FWFTSI", RefSignal => MRSNEg, RefSignalName => "MRSNEg", SetupHigh => tsetup_FWFTSI_MRSNeg_noedge_negedge, SetupLow => tsetup_FWFTSI_MRSNeg_noedge_negedge, CheckEnabled => True, RefTransition => '\', HeaderMsg => InstancePath & partID, TimingData => TD_FWFTSI_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFTSI_MRSNeg); END IF; Violation := Pviol_WCLK OR Pviol_RCLK OR Pviol_MRSNeg OR Pviol_PRSNeg OR Tviol_D0_WCLK OR Tviol_WENNeg_WCLK OR Tviol_RENNeg_RCLK OR Tviol_LDNeg_WCLK OR Tviol_WENNeg_MRSNeg OR Tviol_RENNeg_MRSNeg OR Tviol_LDNeg_MRSNeg OR Tviol_RTNeg_MRSNeg OR Tviol_SENNeg_MRSNeg OR Tviol_WENNeg_PRSNeg OR Tviol_RENNeg_PRSNeg OR Tviol_RTNeg_PRSNeg OR Tviol_SENNeg_PRSNeg OR Rviol_WENNeg_MRSNeg OR Rviol_RENNeg_MRSNeg OR Rviol_LDNeg_MRSNeg OR Rviol_FWFTSI_MRSNeg OR Rviol_WENNeg_PRSNeg OR Rviol_RENNeg_PRSNeg; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorret due timing violation(s)" SEVERITY Warning; END IF; END PROCESS TimingChecks; ------------------------------------------------------------------------ -- Functionality section -- ------------------------------------------------------------------------ -- State Mashine process -- ------------------------------------------------------------------------ FSM: PROCESS (MRSNeg, PRSNeg, WCLK, RCLK) VARIABLE Tf : Time; BEGIN IF MRSNeg = '0' THEN -- master reset occured FIFOWSTATEint <= MRS, NOP AFTER tpw_MRSNeg_negedge; FIFORSTATEint <= MRS, NOP AFTER tpw_MRSNeg_negedge; IF FWFTSI = '0' THEN OpModeint <= '0'; -- Standard mode selected ELSIF FWFTSI = '1' THEN OpModeint <= '1'; -- FWFT mode selected END IF; IF FS = '0' THEN Frequencyint <= '0'; -- RCLK is faster or both clocks are eq ELSIF FS = '1' THEN Frequencyint <= '1'; -- WCLK is faster END IF; ELSIF PRSNeg = '0' THEN -- partial reset occured FIFOWSTATEint <= PRS, NOP AFTER tpw_MRSNeg_negedge; FIFORSTATEint <= PRS, NOP AFTER tpw_MRSNeg_negedge; ELSIF FIFOOperableint THEN IF (WCLK'event AND WCLK = '1') THEN IF WRITEint = '1' AND WRITEPossibleint = '1' THEN -- WRITE FIFOWSTATEint <= WRITE; ELSIF PLOADint = '1' AND PLOADPossibleint = '1' THEN -- PLOAD FIFOWSTATEint <= PLOAD; ELSIF SLOADint = '1' AND SLOADPossibleint = '1' THEN -- SLOAD FIFOWSTATEint <= SLOAD; ELSE FIFOWStateint <= NOP; END IF; END IF; IF (RCLK'event AND RCLK = '1') THEN IF READint = '1' AND READPossibleint = '1' THEN -- READ FIFORSTATEint <= READ; ELSIF PREADint = '1' AND PREADPossibleint = '1' THEN -- PREAD FIFORSTATEint <= PREAD; ELSIF RETRint = '1' AND RETRPossibleint = '1' THEN -- RETRANS IF Frequencyint = '0' THEN -- RCLK is faster or = Tf := tperiod_RCLK_posedge; -- WCLK ELSIF Frequencyint = '1' THEN -- WCLK is faster Tf := tperiod_WCLK_posedge; END IF; IF OpModeint = '0' THEN -- in standard mode FIFORStateint <= RESETUP, NOP AFTER 14*Tf+3*tperiod_RCLK_posedge; ELSIF OpModeInt = '1' THEN -- in FWFT mode FIFORStateint <= RESETUP, NOP AFTER 14*Tf+4*tperiod_RCLK_posedge; END IF; ELSIF FIFORStateint = RESETUP THEN NULL; ELSE FIFORStateint <= NOP; END IF; END IF; ELSE NULL; END IF; END PROCESS FSM; ------------------------------------------------------------------------ -- FIFO Array and registers input/output -- ------------------------------------------------------------------------ FIFOArrayIO: PROCESS (MRSNeg, PRSNEg, LDNeg, WCLK,MAC, RCLK, OffsetRegint, InputLoadedint) VARIABLE FIFOSize : positive; VARIABLE FIFOWordLength : positive; VARIABLE OffsLen : positive := 26; VARIABLE FIFOMemory : FIFOArray := (FIFOArray'range => FIFOWord'(OTHERS => 'X')); VARIABLE Threshold : Natural; VARIABLE Tf : Time; BEGIN IF MAC = '0' THEN-- FIFOSize := FIFOShortSize; FIFOWordLength := FIFOLONGWordLength; OffsLen := OffsSHORTLen; ELSIF MAC = '1' THEN-- FIFOSize := FIFOLONGSize; FIFOWordLength := FIFOSHORTWordLength; OffsLen := OffsLongLen; END IF; IF ( MRSNeg = '0') OR -- MRS ( PRSNeg = '0') THEN -- PRS READPtrint <= 0; -- reset read pointer WRITEPtrint <= 0; -- reset write pointer OutputRegint <= (OTHERS => '0'); FWPassedint <= '0'; RdOffsRegPtrint <= OffsetRegint'low; -- read offs reg ptr WrOffsRegPtrint <= OffsetRegint'low; -- write offs reg ptr StillNoReadint <= '1'; -- set still no read flag RTSCompletedint <= '0'; IF MRSNeg = '0' THEN -- LD input processing during MRS (only) ParaLoadingint <= NOT LDNeg; -- define offset parallel load SeriLoadingint <= LDNeg; -- define offset serial load IF LDNeg = '0' THEN Threshold := LD0DefThreshold; ELSIF LDNeg = '1' THEN Threshold := LD1DefThreshold; ELSE NULL; END IF; OffsetRegint(Offslen-1 DOWNTO 0) <= to_slv(Threshold, OffsLen/2) & -- def PAF offs⌨️ 快捷键说明
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