idt72264.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
-- File name : idt72264.vhd 
--------------------------------------------------------------------------------
--  Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/
--  Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT
--  and supported by Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no
--  warranty with respect to the information contained herein. IDT DISCLAIMS
--  AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING
--  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE
--  ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN
--  NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN
--  CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,
--  CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR
--  APPLICATION OF THE VHDL model. Further, IDT reserves the right to make
--  changes without notice to any product herein to improve reliability,
--  function, or design.  IDT does not convey any license under patent rights
--  or any other intellectual property rights, including those of third parties.
--  IDT is not obligated to provide maintenance or support for the licensed VHDL
--  model.
--
-- MODIFICATION HISTORY :
--
-- version |       author                 |mod date   | changes made
--   V1.0  | PAV & Mikhail V.Alexandrowich| 98 May 01 | initial release
--   V1.1  | R. Munden  | 02 MAY 19 | licensing changed to GPL
--
-- PART DESCRIPTION :
--
-- Library:     FIFO
-- Technology:  CMOS
-- Part:        IDT72264
--
-- Description:   Variable width SuperSync FIFO 8192 x18 or 16384 x9
--------------------------------------------------------------------------------

LIBRARY ieee;   USE ieee.std_logic_1164.ALL;
                USE ieee.vital_primitives.ALL;
                USE ieee.vital_timing.ALL;

LIBRARY fmf;    USE fmf.ff_package.ALL;
                USE fmf.gen_utils.ALL;
                USE fmf.conversions.to_nat;
                USE fmf.conversions.to_slv;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION                                                         --
--------------------------------------------------------------------------------
ENTITY IDT72264 IS
    GENERIC (

         -- tipd delays: interconnect path delays
         --              (there must be one generic for each input pin)

         tipd_D0       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D1       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D2       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D3       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D4       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D5       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D6       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D7       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D8       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D9       : VitalDelayType01 := VitalZeroDelay01;
         tipd_D10      : VitalDelayType01 := VitalZeroDelay01;
         tipd_D11      : VitalDelayType01 := VitalZeroDelay01;
         tipd_D12      : VitalDelayType01 := VitalZeroDelay01;
         tipd_D13      : VitalDelayType01 := VitalZeroDelay01;
         tipd_D14      : VitalDelayType01 := VitalZeroDelay01;
         tipd_D15      : VitalDelayType01 := VitalZeroDelay01;
         tipd_D16      : VitalDelayType01 := VitalZeroDelay01;
         tipd_D17      : VitalDelayType01 := VitalZeroDelay01;
         tipd_MRSNeg   : VitalDelayType01 := VitalZeroDelay01;
         tipd_PRSNeg   : VitalDelayType01 := VitalZeroDelay01;
         tipd_RTNeg    : VitalDelayType01 := VitalZeroDelay01;
         tipd_FWFTSI   : VitalDelayType01 := VitalZeroDelay01;
         tipd_WCLK     : VitalDelayType01 := VitalZeroDelay01;
         tipd_WENNeg   : VitalDelayType01 := VitalZeroDelay01;
         tipd_RCLK     : VitalDelayType01 := VitalZeroDelay01;
         tipd_RENNeg   : VitalDelayType01 := VitalZeroDelay01;
         tipd_OENeg    : VitalDelayType01 := VitalZeroDelay01;
         tipd_SENNeg   : VitalDelayType01 := VitalZeroDelay01;
         tipd_LDNeg    : VitalDelayType01 := VitalZeroDelay01;
         tipd_FS       : VitalDelayType01 := VitalZeroDelay01;
         tipd_MAC      : VitalDelayType01 := VitalZeroDelay01;

         -- tpd delays: propagation delays

         -- tRSF (applicable for all flags)
         tpd_MRSNeg_HFNeg   : VitalDelayType01 := UnitDelay01;
         -- tRSF
         tpd_MRSNeg_Q0 : VitalDelayType01Z := UnitDelay01Z;
         -- tA   (applicable for RCLKxQ-valid
         tpd_RCLK_Q0      : VitalDelayType01Z := UnitDelay01Z;
         -- tOE/tOHZ
         tpd_OENeg_Q0     : VitalDelayType01Z := UnitDelay01Z;
         
         -- tWFF
         tpd_WCLK_FFIRNeg : VitalDelayType01 := UnitDelay01;
         -- tREF
         tpd_RCLK_EFORNEg : VitalDelayType01 := UnitDelay01;
         -- tPAF
         tpd_WCLK_PAFNeg  : VitalDelayType01 := UnitDelay01;
         -- tPAE
         tpd_RCLK_PAENeg  : VitalDelayType01 := UnitDelay01;
         -- tHF (applicable for both WCLK and RCLK)
         tpd_RCLK_HFNEg    : VitalDelayType01 := UnitDelay01;

         -- tpw values: pulse widths
         -- tRCLKH
         tpw_RCLK_posedge   : VitalDelayType := UnitDelay;
         -- tRCLKL
         tpw_RCLK_negedge   : VitalDelayType := UnitDelay;
         -- tWCLKH
         tpw_WCLK_posedge   : VitalDelayType := UnitDelay;
         -- tWCLKL
         tpw_WCLK_negedge   : VitalDelayType := UnitDelay;
         -- tRS   (applicable for both MRS and PRS)
         tpw_MRSNeg_negedge : VitalDelayType := UnitDelay;

         -- tperiod values: min calculated as 1/max freq
         -- tperiod_RCLK_posedge
         tperiod_RCLK_posedge : VitalDelayType := UnitDelay;
         -- tWCLK
         tperiod_WCLK_posedge : VitalDelayType := UnitDelay;

         -- tsetup values: setup times
         -- tDS   (applicable for D/WCLK)
         tsetup_D0_WCLK_noedge_posedge       : VitalDelayType := UnitDelay;
         
         -- tENS
         tsetup_RENNeg_RCLK_noedge_posedge   : VitalDelayType := UnitDelay;

         -- tLDS  (applicable for LDNeg/WCLK)
         tsetup_LDNeg_WCLK_noedge_posedge    : VitalDelayType := UnitDelay;
         tsetup_LDNeg_RCLK_noedge_posedge    : VitalDelayType := UnitDelay;

         -- tRSS  (applicable for REN,WEN,LD,RT,SEN/MRS and REN,WEN,RT,SEN/PRS)
         tsetup_LDNeg_MRSNeg_noedge_posedge   : VitalDelayType := UnitDelay;

         -- tFWFT (applicable for FWFTSI\MRSNeg
         tsetup_FWFTSI_MRSNeg_noedge_negedge : VitalDelayType := UnitDelay;

         -- thold values: hold times
         -- tDH   (applicable for D/WCLK)
         thold_D0_WCLK_noedge_posedge       : VitalDelayType := UnitDelay;
         -- tENH  (applicable for both WEN/WCLK and REN/RCLK)
         thold_RENNeg_RCLK_noedge_posedge   : VitalDelayType := UnitDelay;

         -- tLDH  (applicable for both LDNeg/WCLK and LDNeg/RCLK)
         thold_LDNeg_RCLK_noedge_posedge    : VitalDelayType := UnitDelay;
         thold_LDNeg_WCLK_noedge_posedge    : VitalDelayType := UnitDelay;

         -- tskew values(Not_noedge_posedge: these values are passed through the
         --                    SDF DEVICE construct)

         -- tSKEW1 (skew time /RCLK/WCLK(for FFIR)
         tdevice_SKEW1 : VitalDelayType := UnitDelay;
         -- tSKEW2 (skew time /RCLK/WCLK(for PAE&PAF)
         tdevice_SKEW2  : VitalDelayType := UnitDelay;

         -- generic control parameters

         InstancePath   : STRING  := DefaultInstancePath;
         TimingChecksOn : BOOLEAN := DefaultTimingChecks;
         MsgOn          : BOOLEAN := DefaultMsgOn;
         XOn            : BOOLEAN := DefaultXOn;
         TimingModel    : STRING  := DefaultTimingModel
       );

    PORT (
        D0       : IN  std_logic := 'X';  -----------------------------
        D1       : IN  std_logic := 'X';  --
        D2       : IN  std_logic := 'X';  --
        D3       : IN  std_logic := 'X';  --
        D4       : IN  std_logic := 'X';  --
        D5       : IN  std_logic := 'X';  --
        D6       : IN  std_logic := 'X';  --
        D7       : IN  std_logic := 'X';  --
        D8       : IN  std_logic := 'X';  --
        D9       : IN  std_logic := 'X';  -- Data Input Bus
        D10      : IN  std_logic := 'X';  --
        D11      : IN  std_logic := 'X';  --
        D12      : IN  std_logic := 'X';  --
        D13      : IN  std_logic := 'X';  --
        D14      : IN  std_logic := 'X';  --
        D15      : IN  std_logic := 'X';  --
        D16      : IN  std_logic := 'X';  --
        D17      : IN  std_logic := 'X';  -----------------------------
        MRSNeg   : IN  std_logic := 'X';  -- Master Reset
        PRSNeg   : IN  std_logic := 'X';  -- Partial Reset
        RTNeg    : IN  std_logic := 'X';  -- Retransmit
        FWFTSI   : IN  std_logic := 'X';  -- First Word Fall Trough/Serial In
        WCLK     : IN  std_logic := 'X';  -- Write Clock
        WENNeg   : IN  std_logic := 'X';  -- Write Enable
        RCLK     : IN  std_logic := 'X';  -- Read Clock
        RENNeg   : IN  std_logic := 'X';  -- Read Enable
        OENeg    : IN  std_logic := 'X';  -- Output Enable
        SENNeg   : IN  std_logic := 'X';  -- Serial Enable
        LDNeg    : IN  std_logic := 'X';  -- Load
        MAC      : IN  std_logic := 'X';  -- Memory Array Configuration
        FS       : IN  std_logic := 'X';  -- Frequency Select
        FFIRNeg  : OUT std_logic := 'U';  -- Full Flag/Input Ready
        EFORNeg  : OUT std_logic := 'U';  -- Empty Flag/Output Ready
        PAFNeg   : OUT std_logic := 'U';  -- Programmable Almost Full Flag
        PAENeg   : OUT std_logic := 'U';  -- Programmable Almost Empty Flag
        HFNeg    : OUT std_logic := 'U';  -- Programmable Almost Empty Flag
        Q0       : OUT std_logic := 'U';  ---------------------------------
        Q1       : OUT std_logic := 'U';  --
        Q2       : OUT std_logic := 'U';  --
        Q3       : OUT std_logic := 'U';  --
        Q4       : OUT std_logic := 'U';  --
        Q5       : OUT std_logic := 'U';  --
        Q6       : OUT std_logic := 'U';  --
        Q7       : OUT std_logic := 'U';  --
        Q8       : OUT std_logic := 'U';  -- Data Output Bus
        Q9       : OUT std_logic := 'U';  --
        Q10      : OUT std_logic := 'U';  --
        Q11      : OUT std_logic := 'U';  --
        Q12      : OUT std_logic := 'U';  --
        Q13      : OUT std_logic := 'U';  --
        Q14      : OUT std_logic := 'U';  --
        Q15      : OUT std_logic := 'U';  --
        Q16      : OUT std_logic := 'U';  --
        Q17      : OUT std_logic := 'U'
     ); ---------------------------------

    ATTRIBUTE vital_level0 OF IDT72264 : ENTITY IS True;

END IDT72264;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION                                                   --
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF IDT72264 IS
    ATTRIBUTE vital_level0 OF vhdl_behavioral : ARCHITECTURE IS True;

    CONSTANT partID : String := "IDT72264";

  -- delayed inputs (func. sec. must use these signals instead of actual inputs)
    SIGNAL D0_ipd     : std_ulogic := 'X';
    SIGNAL D1_ipd     : std_ulogic := 'X';
    SIGNAL D2_ipd     : std_ulogic := 'X';
    SIGNAL D3_ipd     : std_ulogic := 'X';
    SIGNAL D4_ipd     : std_ulogic := 'X';
    SIGNAL D5_ipd     : std_ulogic := 'X';
    SIGNAL D6_ipd     : std_ulogic := 'X';
    SIGNAL D7_ipd     : std_ulogic := 'X';
    SIGNAL D8_ipd     : std_ulogic := 'X';
    SIGNAL D9_ipd     : std_ulogic := 'X';
    SIGNAL D10_ipd    : std_ulogic := 'X';
    SIGNAL D11_ipd    : std_ulogic := 'X';
    SIGNAL D12_ipd    : std_ulogic := 'X';
    SIGNAL D13_ipd    : std_ulogic := 'X';
    SIGNAL D14_ipd    : std_ulogic := 'X';
    SIGNAL D15_ipd    : std_ulogic := 'X';
    SIGNAL D16_ipd    : std_ulogic := 'X';
    SIGNAL D17_ipd    : std_ulogic := 'X';
    SIGNAL MRSNeg_ipd : std_ulogic := 'X';
    SIGNAL PRSNeg_ipd : std_ulogic := 'X';
    SIGNAL RTNeg_ipd  : std_ulogic := 'X';
    SIGNAL FWFTSI_ipd : std_ulogic := 'X';
    SIGNAL WCLK_ipd   : std_ulogic := 'X';
    SIGNAL WENNeg_ipd : std_ulogic := 'X';
    SIGNAL RCLK_ipd   : std_ulogic := 'X';
    SIGNAL RENNeg_ipd : std_ulogic := 'X';
    SIGNAL OENeg_ipd  : std_ulogic := 'X';
    SIGNAL SENNeg_ipd : std_ulogic := 'X';
    SIGNAL LDNeg_ipd  : std_ulogic := 'X';
    SIGNAL MAC_ipd    : std_ulogic := 'X';
    SIGNAL FS_ipd     : std_ulogic := 'X';
    -- FIFO memory definitions

    CONSTANT FIFOSHORTSize       :  positive := 8192;  --if MAC = 0--
    CONSTANT FIFOLONGSize        :  positive := 16384; --if MAC = 1--
    CONSTANT FIFOLONGWordLength  :  positive := 18;    --if MAC = 0--
    CONSTANT FIFOSHORTWordLength :  positive := 9;     --if MAC = 1 --
    CONSTANT LD0DefThreshold     :  positive := 127;  -- when LD = 0
    CONSTANT LD1DefThreshold     :  positive := 1023; -- when LD = 1
    CONSTANT OffsSHORTLen        :  positive := 26; 
                                     -- PAF&PAE Offset reg length if MAC = 0
    CONSTANT OffsLONGLen         :  positive := 28;
                                     -- PAF&PAE Offset reg length if MAC=1
    SUBTYPE  FIFOWord        IS Std_Logic_Vector(FIFOLONGWordLength-1 DOWNTO 0);
    TYPE     FIFOArray       IS ARRAY (0 TO FIFOLONGSize - 1) OF FIFOWord;

    TYPE     FIFOStates      IS (UNKNOWN,
                                 MRS,
                                 PRS,
                                 WRITE,
                                 RESETUP,
                                 READ,
                                 SLOAD,
                                 PLOAD,
                                 PREAD,
                                 NOP);

    -- internal signals

    SIGNAL FIFOOperableint : Boolean;              -- FOFO operability flag
    SIGNAL READPtrint      : Natural RANGE 0 TO FIFOLONGSize-1;
    SIGNAL WRITEPtrint     : Natural RANGE 0 TO FIFOLONGSize-1;
    SIGNAL FIFOWSTATEint   : FIFOStates := UNKNOWN;-- FIFO FSM state(acc WCLK)
    SIGNAL FIFORSTATEint   : FIFOStates := UNKNOWN;-- FIFO FSM state(acc RCLK)
    SIGNAL OpModeint       : std_ulogic := 'X'; -- op mode: '0'-std, '1'-FWFT
    SIGNAL Frequencyint    : std_ulogic := 'X'; -- selected frequency