idt72255.ftm
来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 156 行
FTM
156 行
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT72255 Parts</TITLE><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 99 MAY 25 Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT72255<FMFTIME>IDT72255L10PF<SOURCE>IDT data sheet November 1998</SOURCE>IDT72255L10TF<SOURCE>IDT data sheet November 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK EFORNeg (2:6:8) (2:6:8)) (IOPATH RCLK PAENeg (2:6:8) (2:6:8)) (IOPATH MRSNeg HFNeg (3:8:10) (3:8:10)) (IOPATH RCLK HFNeg (3:12:16) (3:12:16)) (IOPATH WCLK PAFNeg (2:6:8) (2:6:8)) (IOPATH WCLK FFIRNeg (2:6:8) (2:6:8)) (IOPATH MRSNeg Q0 (3:8:10) (3:8:10) (3:8:10) (3:8:10) (3:8:10) (3:8:10)) (IOPATH RCLK Q0 (2:6:8) (2:6:8) (2:6:8) (2:6:8) (2:6:8) (2:6:8)) (IOPATH OENeg Q0 (3:6:7) (3:6:7) (3:6:7) (3:6:7) (3:6:7) (3:6:7)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (10)) (PERIOD (posedge WCLK) (10)) (WIDTH (posedge RCLK) (4.5)) (WIDTH (negedge RCLK) (4.5)) (WIDTH (posedge WCLK) (4.5)) (WIDTH (negedge WCLK) (4.5)) (WIDTH (negedge MRSNeg) (10)) (SETUPHOLD D0 (posedge WCLK) (3.5) (0)) (SETUPHOLD RENNeg (posedge RCLK) (3.5) (0)) (SETUPHOLD LDNeg (posedge WCLK) (3.5) (6.5)) (SETUP LDNeg (posedge MRSNeg) (10)) (SETUP FWFTSI (negedge MRSNeg) (0)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (8) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (15) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72255L12PF<SOURCE>IDT data sheet November 1998</SOURCE>IDT72255L12TF<SOURCE>IDT data sheet November 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK EFORNeg (2:7:9) (2:7:9)) (IOPATH RCLK PAENeg (2:7:9) (2:7:9)) (IOPATH MRSNeg HFNeg (3:9:12) (3:9:12)) (IOPATH RCLK HFNeg (4:13:20) (4:13:20)) (IOPATH WCLK PAFNeg (2:7:9) (2:7:9)) (IOPATH WCLK FFIRNeg (2:7:9) (2:7:9)) (IOPATH MRSNeg Q0 (3:9:12) (3:9:12) (3:9:12) (3:9:12) (3:9:12) (3:9:12)) (IOPATH RCLK Q0 (2:7:9) (2:7:9) (2:7:9) (2:7:9) (2:7:9) (2:7:9)) (IOPATH OENeg Q0 (3:6:7.5) (3:6:7.5) (3:6:7.5) (3:6:7.5) (3:6:7.5) (3:6:7.5)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (12)) (PERIOD (posedge WCLK) (12)) (WIDTH (posedge RCLK) (5)) (WIDTH (negedge RCLK) (5)) (WIDTH (posedge WCLK) (5)) (WIDTH (negedge WCLK) (5)) (WIDTH (negedge MRSNeg) (12)) (SETUPHOLD D0 (posedge WCLK) (3.5) (0)) (SETUPHOLD RENNeg (posedge RCLK) (3.5) (0)) (SETUPHOLD LDNeg (posedge WCLK) (3.5) (8.5)) (SETUP LDNeg (posedge MRSNeg) (12)) (SETUP FWFTSI (negedge MRSNeg) (0)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (10) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (18) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72255L15PF<SOURCE>IDT data sheet November 1998</SOURCE>IDT72255L15TF<SOURCE>IDT data sheet November 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK EFORNeg (3:8:10) (3:8:10)) (IOPATH RCLK PAENeg (3:8:10) (3:8:10)) (IOPATH MRSNeg HFNeg (3:10:15) (3:10:15)) (IOPATH RCLK HFNeg (4:13:20) (4:13:20)) (IOPATH WCLK PAFNeg (3:8:10) (3:8:10)) (IOPATH WCLK FFIRNeg (3:8:10) (3:8:10)) (IOPATH MRSNeg Q0 (3:10:15)(3:10:15)(3:10:15)(3:10:15)(3:10:15)(3:10:15)) (IOPATH RCLK Q0 (2:6:10) (2:6:10) (2:6:10) (2:6:10) (2:6:10) (2:6:10)) (IOPATH OENeg Q0 (3:6:8) (3:6:8) (3:6:8) (3:6:8) (3:6:8) (3:6:8)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (15)) (PERIOD (posedge WCLK) (15)) (WIDTH (posedge RCLK) (6)) (WIDTH (negedge RCLK) (6)) (WIDTH (posedge WCLK) (6)) (WIDTH (negedge WCLK) (6)) (WIDTH (negedge MRSNeg) (15)) (SETUPHOLD D0 (posedge WCLK) (4) (1)) (SETUPHOLD RENNeg (posedge RCLK) (4) (1)) (SETUPHOLD LDNeg (posedge WCLK) (4) (10)) (SETUP LDNeg (posedge MRSNeg) (15)) (SETUP FWFTSI (negedge MRSNeg) (0)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (12) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (21) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72255L20PF<SOURCE>IDT data sheet November 1998</SOURCE>IDT72255L20TF<SOURCE>IDT data sheet November 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RCLK EFORNeg (3:8:12) (3:8:12)) (IOPATH RCLK PAENeg (3:8:12) (3:8:12)) (IOPATH MRSNeg HFNeg (4:12:20) (4:12:20)) (IOPATH RCLK HFNeg (4:13:22) (4:13:22)) (IOPATH WCLK PAFNeg (3:8:12) (3:8:12)) (IOPATH WCLK FFIRNeg (3:8:12) (3:8:12)) (IOPATH MRSNeg Q0 (4:12:20) (4:12:20) (4:12:20) (4:12:20) (4:12:20) (4:12:20)) (IOPATH RCLK Q0 (2:6:12) (2:6:12) (2:6:12) (2:6:12) (2:6:12) (2:6:12)) (IOPATH OENeg Q0 (3:8:10) (3:8:10) (3:8:10) (3:8:10) (3:8:10) (3:8:10)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (20)) (PERIOD (posedge WCLK) (20)) (WIDTH (posedge RCLK) (8)) (WIDTH (negedge RCLK) (8)) (WIDTH (posedge WCLK) (8)) (WIDTH (negedge WCLK) (8)) (WIDTH (negedge MRSNeg) (20)) (SETUPHOLD D0 (posedge WCLK) (5) (1)) (SETUPHOLD RENNeg (posedge RCLK) (5) (1)) (SETUPHOLD LDNeg (posedge WCLK) (5) (10)) (SETUP LDNeg (posedge MRSNeg) (20)) (SETUP FWFTSI (negedge MRSNeg) (0)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (15) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (25) ) ) )</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
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