cy7c443.vhd

VHDL的ram和fifo model code 包含众多的厂家

                    RefSignalName   => "CKW",
                    SetupHigh       => tsetup_D0_CKW,
                    SetupLow        => tsetup_D0_CKW,
                    HoldHigh        => thold_D0_CKW,
                    HoldLow         => thold_D0_CKW,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_D0_CKW,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_CKW);

                VitalSetupHoldCheck (
                    TestSignal      => ENWNeg,
                    TestSignalName  => "ENWNeg",
                    RefSignal       => CKW,
                    RefSignalName   => "CKW",
                    SetupHigh       => tsetup_ENWNeg_CKW,
                    SetupLow        => tsetup_ENWNeg_CKW,
                    HoldHigh        => thold_ENWNeg_CKW,
                    HoldLow         => thold_ENWNeg_CKW,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ENWNeg_CKW,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ENWNeg_CKW );

                VitalSetupHoldCheck (
                    TestSignal      => ENRNeg,
                    TestSignalName  => "ENRNeg",
                    RefSignal       => CKR,
                    RefSignalName   => "CKR",
                    SetupHigh       => tsetup_ENWNeg_CKW,
                    SetupLow        => tsetup_ENWNeg_CKW,
                    HoldHigh        => thold_ENWNeg_CKW,
                    HoldLow         => thold_ENWNeg_CKW,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_ENRNeg_CKR,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_ENRNeg_CKR );

                VitalSetupHoldCheck (
                    TestSignal      => CKW,
                    TestSignalName  => "RNeg",
                    RefSignal       => MRNeg,
                    RefSignalName   => "MRNeg",
                    SetupLow        => tsetup_CKW_MRNeg,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CKW_MRNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CKW_MRNeg );

                VitalSetupHoldCheck (
                    TestSignal      => CKR,
                    TestSignalName  => "RNeg",
                    RefSignal       => MRNeg,
                    RefSignalName   => "MRNeg",
                    SetupLow        => tsetup_CKW_MRNeg,
                    CheckEnabled    => TRUE,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_CKR_MRNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_CKR_MRNeg );


                VitalPeriodPulseCheck (
                    TestSignal      =>  CKR,
                    TestSignalName  =>  "CKR",
                    Period          =>  tperiod_CKR,
                    PulseWidthLow   =>  tpw_CKR_negedge,
                    PulseWidthHigh  =>  tpw_CKR_posedge,
                    PeriodData      =>  TD_CKR,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE,
                    Violation       =>  Pviol_CKR );

                VitalPeriodPulseCheck (
                    TestSignal      =>  CKW,
                    TestSignalName  =>  "CKW",
                    Period          =>  tperiod_CKR,
                    PulseWidthLow   =>  tpw_CKR_negedge,
                    PulseWidthHigh  =>  tpw_CKR_posedge,
                    PeriodData      =>  TD_CKW,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE,
                    Violation       =>  Pviol_CKW );

                VitalPeriodPulseCheck (
                    TestSignal      =>  MRNeg,
                    TestSignalName  =>  "MRNeg",
                    PulseWidthLow   =>  tpw_MRNeg_negedge,
                    PeriodData      =>  TD_MRNeg,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  TRUE,
                    Violation       =>  Pviol_MRNeg );
    
               VitalRecoveryRemovalCheck (
                    TestSignal      => CKW,
                    TestSignalName  => "CKW",
                    RefSignal       => MRNeg,
                    RefSignalName   => "MRNeg",
                    Recovery        => trecovery_CKW_MRNeg,
                    ActiveLow       => FALSE,
                    CheckEnabled    => TRUE,
                    RefTransition    => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => RD_CKW_MRNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Rviol_CKW_MRNeg);

                VitalRecoveryRemovalCheck (
                    TestSignal      => CKR,
                    TestSignalName  => "CKR",
                    RefSignal       => MRNeg,
                    RefSignalName   => "MRNeg",
                    Recovery        => trecovery_CKW_MRNeg,
                    ActiveLow       => FALSE,
                    CheckEnabled    => TRUE,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => RD_CKR_MRNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Rviol_CKR_MRNeg);
  
        Violation := Tviol_D0_CKW        OR 
                     Pviol_CKR           OR
                     Pviol_CKW           OR 
                     Pviol_MRNeg         OR
                     Rviol_CKW_MRNeg     OR
                     Rviol_CKR_MRNeg;

            ASSERT   Violation = '0'
            REPORT   InstancePath & partID & " : signal values may be" &
                     " incorrect due timing violation(s)"
            SEVERITY Warning;

          END IF; -- Timing Check Section

        ---------------------------------------------------------------
        -- Functionality section
        ---------------------------------------------------------------

            IF falling_edge(MRNeg) THEN
                Start <= '0';
                CountPointer <= 0;
            ELSIF rising_edge(MRNeg) THEN
                F1_zd  <= '0';
                F2_zd  <= '0';
                Start <= '1';
                rd_stat := act;
                wr_stat := act;
                Q_zd <= (OTHERS => '0');
            END IF;
   
            IF Start = '1' THEN   -- Read/Write Cycles
            -- Write Cycle
                IF rising_edge(CKW) AND ENWNeg ='0' THEN 
                    IF wr_stat=act THEN                           
                        IF CountPointer >=  (FIFOSize - FullOffReg - 1) THEN
                            IF tSKEW_CKR_CKW >= tSKEW2 THEN F1_zd <= '0';
                            ELSE F1_zd <= '0' AFTER (tCKW);
                            END IF;
                            IF tSKEW_CKR_CKW >= tSKEW2 THEN F2_zd <= '1';
                            ELSE F2_zd <= '1' AFTER (tCKW);
                            END IF;
                        ELSIF CountPointer > EmptyOffReg- 1   THEN
                            IF tSKEW_CKR_CKW >= tSKEW2 THEN F1_zd <= '1';
                            ELSE F1_zd <= '1' AFTER (tCKW);
                            END IF;
                            IF tSKEW_CKR_CKW >= tSKEW2 THEN F2_zd <= '1';
                            ELSE F2_zd <= '1' AFTER (tCKW);
                            END IF;
                        ELSIF CountPointer = FIFOSize THEN
                            wr_stat:=inact;
                        END IF;
                        IF Violation = '0' THEN
                            FIFOMemory(CountPointer) := to_nat(Data);
                        ELSE
                           FIFOMemory(CountPointer) := -1;
                        END IF;
                        CountPointer <= CountPointer + 1;
                        rd_stat:=act;
                    END IF;
                END IF;  -- End of Write Cycle

                   -- Read Cycle
                IF rising_edge(CKR) AND ENRNeg = '0' THEN 
                    IF  rd_stat=act THEN
                        IF CountPointer = 1 THEN
                            IF tSKEW_CKW_CKR >= tSKEW1 THEN F1_zd <= '0';  
                            ELSE F1_zd <= '0' AFTER (tCKR);
                            END IF;
                            IF tSKEW_CKW_CKR >= tSKEW1 THEN F2_zd <= '0';  
                            ELSE F2_zd <= '0' AFTER (tCKR);
                            END IF;
                        ELSIF CountPointer <= EmptyOffReg + 1 THEN
                            IF tSKEW_CKW_CKR >= tSKEW1 THEN F1_zd <= '1';  
                            ELSE F1_zd <= '1' AFTER (tCKR);
                            END IF;
                            IF tSKEW_CKW_CKR >= tSKEW1 THEN F2_zd <= '0';  
                            ELSE F2_zd <= '0' AFTER (tCKR);
                            END IF;
                        ELSE
                            IF tSKEW_CKW_CKR >= tSKEW1 THEN F1_zd <= '1';  
                            ELSE F1_zd <= '1' AFTER (tCKR);
                            END IF;
                            IF tSKEW_CKW_CKR >= tSKEW1 THEN F2_zd <= '1';  
                            ELSE F2_zd <= '1' AFTER (tCKR);
                            END IF;
                        END IF;
                        IF FIFOMemory(0)>=0 THEN
                            Q_zd <= to_slv(FIFOMemory(0),9);
                        ELSE
                            Q_zd<=(OTHERS=>'X');
                        END IF;
                        CountPointer <= CountPointer - 1;
                        IF CountPointer=0 THEN 
                            rd_stat:=inact; 
                        END IF;
                        FOR i IN 0 TO CountPointer - 1 LOOP
                            FIFOMemory(i) := FIFOMemory(i + 1);
                        END LOOP;
                    END IF;
                END IF; -- End of Read Cycle
            END IF;    -- End of Start 
        
        END PROCESS MainReadWrite;

        ------------------------------------------------------------------------
        -- Detection of the actual tSKEW vals                                --
        ------------------------------------------------------------------------

        SkewDetector: PROCESS(CKR, CKW)

            VARIABLE tCKRposedge : Time := 0 ns;
            VARIABLE tCKWposedge : Time := 0 ns;

        BEGIN

            IF CKR'event AND CKR = '1'
            THEN tCKRposedge := Now;
                 tSKEW_CKW_CKR <= Now - tCKWposedge;
            END IF;

            IF CKW'event AND CKW = '1'
            THEN tCKWposedge := Now;
                 tSKEW_CKR_CKW <= Now - tCKRposedge;
            END IF;

        END PROCESS SkewDetector;
  
        ------------------------------------------------------------------------
        -- Path delay section                                                 --
        ------------------------------------------------------------------------

        -- Path Delay for F1
        F1PathDelay: PROCESS (F1_zd)

        VARIABLE F1_GlitchData  : VitalGlitchDataType;
        BEGIN
            VitalPathDelay01
                (OutSignal     => F1,
                 OutSignalName => "F1",
                 OutTemp       => F1_zd,
                 GlitchData    => F1_GlitchData,
                 Paths         => (0 => (InputChangeTime => MRNeg'last_event,
                                        PathDelay       => tpd_MRNeg_F1,
                                        PathCondition   => true),
                                  1 => (InputChangeTime => CKR'last_event,
                                        PathDelay       => tpd_CKW_F1,
                                        PathCondition   => CKR='1'),
                                  2 => (InputChangeTime => CKW'last_event,
                                        PathDelay       => tpd_CKW_F1,
                                        PathCondition   => CKR='1')));
         END PROCESS F1PathDelay;  
         
        -- Path Delay for F2
        F2PathDelay: PROCESS (F2_zd)

        VARIABLE F2_GlitchData  : VitalGlitchDataType;
        BEGIN
            VitalPathDelay01
                (OutSignal     => F2,
                 OutSignalName => "F2",
                 OutTemp       => F2_zd,
                 GlitchData    => F2_GlitchData,
                 Paths         => (0 => (InputChangeTime => MRNeg'last_event,
                                        PathDelay       => tpd_MRNeg_F1,
                                        PathCondition   => true),
                                  1 => (InputChangeTime => CKR'last_event,
                                        PathDelay       => tpd_CKW_F1,
                                        PathCondition   => CKW='1'),
                                  2 => (InputChangeTime => CKW'last_event,
                                        PathDelay       => tpd_CKW_F1,
                                        PathCondition   => CKR='1')));

         END PROCESS F2PathDelay;  
         
        -- Path Delay for Output Q
        QPathDelay_Gen: FOR i IN FIFOWordLength-1 DOWNTO 0 GENERATE
             
         PROCESS (Q_zd(i))
             
         VARIABLE Q_GlitchData  : VitalGlitchDataType;
         BEGIN

             VitalPathDelay01
                 (OutSignal     => Q(i),
                  OutSignalName => "Q",
                  OutTemp       => Q_zd(i),
                  GlitchData    => Q_GlitchData,
                  Paths         => (0 => (InputChangeTime => MRNeg'last_event,
                                         PathDelay       => tpd_MRNeg_Q0,
                                         PathCondition   => true),
                                   1 => (InputChangeTime => CKR'last_event,
                                         PathDelay       => tpd_CKR_Q0,
                                         PathCondition   => true)));
        END PROCESS;

       END GENERATE QPathDelay_Gen;
    END BLOCK VitalBehavior;
END vhdl_behavioral;