idt72v205.vhd

VHDL的ram和fifo model code 包含众多的厂家

                MsgOn           => MsgOn,
                Violation       => Tviol_D0_WCLK);
            END IF;

            --7 WENNeg/WCLK setup/hold time check (tENS, tENH)
            IF WENNeg'event OR (WCLK'event AND WCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => WENNEg,
                TestSignalName  => "WENNeg",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupLow        => tsetup_RENNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_RENNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WENNeg_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WENNeg_WCLK);
            END IF;

            --8 RENNeg/RCLK setup/hold time check (tENS, tENH)
            IF RENNeg'event OR (RCLK'event AND RCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => RENNEg,
                TestSignalName  => "RENNeg",
                RefSignal       => RCLK,
                RefSignalName   => "RCLK",
                SetupLow        => tsetup_RENNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_RENNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_RENNeg_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RENNeg_RCLK);
            END IF;

            --9 LDNeg/WCLK setup/hold time check (tLDS, tLDH)
            IF LDNeg'event OR (WCLK'event AND WCLK = '1' AND WENNeg ='0') THEN

            VitalSetupHoldCheck (
                TestSignal      => LDNEg,
                TestSignalName  => "LDNeg",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupLow        => tsetup_RENNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_RENNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LDNeg_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LDNeg_WCLK);
            END IF;

            --10 LDNeg/RCLK setup/hold time check (tLDS, tLDH)
            IF LDNeg'event OR (RCLK'event AND RCLK = '1' AND RENNeg ='0') THEN

            VitalSetupHoldCheck (
                TestSignal      => LDNEg,
                TestSignalName  => "LDNeg",
                RefSignal       => RCLK,
                RefSignalName   => "RCLK",
                SetupLow        => tsetup_RENNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_RENNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LDNeg_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LDNeg_RCLK);
            END IF;

            --11 RENNeg/RSNeg setup time check (tRSS) 
            IF RENNeg'event OR (RSNeg'event AND RSNeg = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => RENNEg,
                TestSignalName  => "RENNeg",
                RefSignal       => RSNEg,
                RefSignalName   => "RSNEg",
                SetupHigh       => tsetup_LDNeg_RSNeg_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_RENNeg_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RENNeg_RSNeg);
            END IF;

            --12 WENNeg/RSNeg setup time check (tRSS)
            IF WENNeg'event OR (RSNeg'event AND RSNeg = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => WENNEg,
                TestSignalName  => "WENNeg",
                RefSignal       => RSNEg,
                RefSignalName   => "RSNEg",
                SetupHigh       => tsetup_LDNeg_RSNeg_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WENNeg_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WENNeg_RSNeg);
            END IF;

            --13 LDNeg/RSNeg setup time check (tRSS)
            IF LDNeg'event OR (RSNeg'event AND RSNeg = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => LDNEg,
                TestSignalName  => "LDNeg",
                RefSignal       => RSNEg,
                RefSignalName   => "RSNEg",
                SetupHigh       => tsetup_LDNeg_RSNeg_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LDNeg_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LDNeg_RSNeg);
            END IF;

            --14 WXINeg/WCLK setup time check (tXIS)
            IF WXINeg'event OR (WCLK'event AND WCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => WXINeg,
                TestSignalName  => "WXINeg",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupLow        => tsetup_RXINeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WXINeg_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WXINeg_WCLK);
            END IF;

            --15 RXINeg/RCLK setup time check (tXIS)
            IF RXINeg'event OR (RCLK'event AND RCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => RXINeg,
                TestSignalName  => "RXINeg",
                RefSignal       => RCLK,
                RefSignalName   => "RCLK",
                SetupLow        => tsetup_RXINeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_RXINeg_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RXINeg_RCLK);
            END IF;

            Violation :=
                Pviol_WCLK            OR
                Pviol_RCLK            OR
                Pviol_RSNeg           OR
                Pviol_WXINeg          OR
                Pviol_RXINeg          OR

                Tviol_D0_WCLK         OR
                Tviol_WENNeg_WCLK     OR
                Tviol_RENNeg_RCLK     OR
                Tviol_LDNeg_WCLK      OR
                Tviol_LDNeg_RCLK      OR
                Tviol_WENNeg_RSNeg    OR
                Tviol_RENNeg_RSNeg    OR
                Tviol_LDNeg_RSNeg     OR
                Tviol_WXINeg_WCLK     OR
                Tviol_RXINeg_RCLK     OR

                Rviol_WENNeg_RSNeg    OR
                Rviol_RENNeg_RSNeg    OR
                Rviol_LDNeg_RSNeg     ;

            ASSERT   Violation = '0'
            REPORT   InstancePath & partID & " : signal values may be" &
                     " incorret due timing violation(s)"
            SEVERITY Warning;

        END IF;

    END PROCESS TimingChecks;

    ----------------------------------------------------------------------------
    -- Functionality section ---------------------------------------------------
    ----------------------------------------------------------------------------

    ----------------------------------------------------------------------------
    -- FIFO Array                                                             --
    ----------------------------------------------------------------------------

    Input_Register: PROCESS (WCLK,Wr_RAM_Onint,D)
    BEGIN
        IF WCLK = '0' THEN
            IF (Wr_RAM_Onint='1') THEN
                Input_Regint <= D;
            END IF;
        END IF;
    END PROCESS;

    Memory: PROCESS(WCLK,Wr_RAM_Onint,Input_Regint,Wr_Pnt_Delint)
    BEGIN
        IF WCLK = '1' THEN
            IF (Wr_RAM_Delint='1') THEN
                RAM (to_nat(Wr_Pnt_Delint)) <= Input_Regint;
            END IF;
        END IF;
    END PROCESS;

    ----------------------------------------------------------------------------
    -- Read/Write Pointer Logic                                               --
    ----------------------------------------------------------------------------

    Wr_RAM_Onint <='1' WHEN (WENNeg='0') and (Fullint='0') and (LDNeg='1') and
                      (Write_Enableint='1') ELSE
                   '0';

    Wr_RAM_Delint <='1' WHEN (WENNeg='0') and (FF_Delint='0') and (LDNeg='1') 
                       and (Write_Enableint='1') ELSE
                   '0';
              

    Rd_RAM_Onint <='1' WHEN (RENNeg='0') and (Emptyint='0') and (LDNeg='1')
                      and (Read_Enableint='1') ELSE
                   '0';


    Write_Pointer_Register: PROCESS (RSNeg, WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Write_PRint <= (others =>'0') ; 
            Write_Flint<='0';
        ELSIF WCLK'event and WCLK='1' THEN
                IF (Wr_RAM_Onint='1') THEN
                    Write_PRint <= to_slv(WritePnt_Sumint,AddrBitNum);
                    Write_Flint<='1';
                ELSE
                    Write_Flint<='0';
                END IF;
        END IF;
    END PROCESS;

    Write_Pointerint <= to_nat(Write_PRint) ;

    WritePnt_Sumint <= Write_Pointerint + 1;

    Write_Pointer_Delayed_Register: PROCESS (RSNeg, WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Wr_Pnt_Delint <= (others =>'0') ;
        ELSIF WCLK'event and WCLK='0' THEN
                Wr_Pnt_Delint <=  Write_PRint;
        END IF;
    END PROCESS;

    Read_Pointer_Register: PROCESS (RSNeg, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Read_PRint <= (others =>'0') ; 
            Read_Flint<='0';
        ELSIF RCLK'event and RCLK='1' THEN
                IF (Rd_RAM_Onint='1') or (Fst_Wrdint ='1') THEN
                    Read_PRint <=  to_slv(Read_Pointerint+1,AddrBitNum);
                    Read_Flint<='1';
                ELSE
                    Read_Flint<='0';
                END IF;
        END IF;
    END PROCESS;

    Read_Pointerint <= to_nat(Read_PRint) ;

    ----------------------------------------------------------------------------
    -- Offset Register Logic                                                  --
    ----------------------------------------------------------------------------

    Wr_Ofs_Onint <='1' WHEN (WENNeg='0') and (LDNeg='0')
                             --and (Write_Enableint='1') --always
                             ELSE
                   '0';
              
    Rd_Ofs_Onint <='1' WHEN (RENNeg='0') and (LDNeg='0') and
                            (Read_Enableint='1')  ELSE  --not always
                   '0';

    PAE_Offset_Register: PROCESS (RSNeg, WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            PAE_Offset_Regint <= to_slv(Default_Val,OffsetLength);
        ELSIF WCLK'event and WCLK='1' THEN
                IF (Wr_Ofs_Onint='1') and (Wr_Offset_Pntint='0') THEN
                    PAE_Offset_Regint <= D (OffsetLength-1 DOWNTO 0);
                END IF;
        END IF;
    END PROCESS;

    PAF_Offset_Register: PROCESS (RSNeg, WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            PAF_Offset_Regint <= to_slv(Default_Val,OffsetLength);
        ELSIF WCLK'event and WCLK='1' THEN
                IF (Wr_Ofs_Onint='1') and (Wr_Offset_Pntint='1')  THEN
                    PAF_Offset_Regint <= D (OffsetLength-1 DOWNTO 0);
                END IF;
        END IF;
    END PROCESS;

    Wr_Offset_Pointer: PROCESS (RSNeg, WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Wr_Offset_Pntint <= '0' ;
        ELSIF WCLK'event and WCLK='1' THEN
                IF (Wr_Ofs_Onint='1') THEN
                    Wr_Offset_Pntint <= not Wr_Offset_Pntint;
                END IF;
        END IF;
    END PROCESS;

    Rd_Offset_Pointer: PROCESS (RSNeg, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Rd_Offset_Pntint <= '0';
        ELSIF RCLK'event and RCLK='1' THEN
                IF (Rd_Ofs_Onint='1')  THEN
                    Rd_Offset_Pntint <= not Rd_Offset_Pntint;
                END IF;
        END IF;
    END PROCESS;

    ----------------------------------------------------------------------------
    -- Flag Logic                                                             --
    ----------------------------------------------------------------------------

    Write_PRint_DEL <= Write_PRint after tdevice_SKEW1;