📄 idt72805.vhd
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---------------------------------------------------------------------------------- File name : idt72805.vhd---------------------------------------------------------------------------------- Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/-- Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT-- and supported by Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no-- warranty with respect to the information contained herein. IDT DISCLAIMS-- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE-- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN-- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN-- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,-- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR-- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make-- changes without notice to any product herein to improve reliability,-- function, or design. IDT does not convey any license under patent rights-- or any other intellectual property rights, including those of third parties.-- IDT is not obligated to provide maintenance or support for the licensed VHDL-- model.---- MODIFICATION HISTORY :---- version | author | mod date | changes made-- V1.0 | Igor Oznobikhin | 98 MAY 13 | initial coding-- V1.1 | R. Munden | 02 MAY 19 | licensing changed to GPL---------------------------------------------------------------------------------- PART DESCRIPTION :---- Library: FIFO-- Technology: CMOS-- Part: IDT72805---- Descripton: DUAL SyncFIFO 256x18-bit--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;LIBRARY FMF; USE FMF.ff_package.ALL; USE FMF.gen_utils.ALL; USE FMF.conversions.to_nat; USE FMF.conversions.to_slv;---------------------------------------------------------------------------------- ENTITY DECLARATION ----------------------------------------------------------------------------------ENTITY IDT72805 IS GENERIC ( -- tipd delays: interconnect path delays -- (there must be one generic for each input pin) tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_RSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_LDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WXINeg : VitalDelayType01 := VitalZeroDelay01; tipd_RXINeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays -- tRSF tpd_RSNeg_EFNeg : VitalDelayType01 := UnitDelay01; -- tRSF tpd_RSNeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tA (applicable for RCLK - Q ) tpd_RCLK_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ/tOE/tOHZ tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tWFF tpd_WCLK_FFNeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_RCLK_EFNeg : VitalDelayType01 := UnitDelay01; -- tPAF tpd_RCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAE tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tHF (applicable for both WCLK and RCLK) tpd_RCLK_WXOHFNeg : VitalDelayType01 := UnitDelay01; -- tXO tpd_RCLK_RXONeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tCLKH tpw_RCLK_posedge : VitalDelayType := UnitDelay; -- tCLKL tpw_RCLK_negedge : VitalDelayType := UnitDelay; -- tRS tpw_RSNeg_negedge : VitalDelayType := UnitDelay; -- tXI tpw_RXINeg_negedge : VitalDelayType := UnitDelay; -- tperiod min (calculated as 1/max freq) -- tCLK (applicable for both WCLK and RCLK) tperiod_RCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENS (applicable for both WEN/WCLK and REN/RCLK) tsetup_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tLDS tsetup_LDNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tRSS (applicable for REN,WEN,LD) tsetup_LDNeg_RSNeg_noedge_posedge : VitalDelayType := UnitDelay; -- tXIS tsetup_RXINeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENH thold_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tLDH thold_LDNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tskew values: skew times -- tSKEW1 tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW2 tdevice_SKEW2 : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_logic := 'X'; -- Data Input Bus D1 : IN std_logic := 'X'; D2 : IN std_logic := 'X'; D3 : IN std_logic := 'X'; D4 : IN std_logic := 'X'; D5 : IN std_logic := 'X'; D6 : IN std_logic := 'X'; D7 : IN std_logic := 'X'; D8 : IN std_logic := 'X'; D9 : IN std_logic := 'X'; D10 : IN std_logic := 'X'; D11 : IN std_logic := 'X'; D12 : IN std_logic := 'X'; D13 : IN std_logic := 'X'; D14 : IN std_logic := 'X'; D15 : IN std_logic := 'X'; D16 : IN std_logic := 'X'; D17 : IN std_logic := 'X'; RSNeg : IN std_logic := 'X'; -- Reset WCLK : IN std_logic := 'X'; -- Write Clock WENNeg : IN std_logic := 'X'; -- Write Enable RCLK : IN std_logic := 'X'; -- Read Clock RENNeg : IN std_logic := 'X'; -- Read Enable OENeg : IN std_logic := 'X'; -- Output Enable LDNeg : IN std_logic := 'X'; -- Load FLNeg : IN std_logic := 'X'; -- First Load WXINeg : IN std_logic := 'X'; -- Write Expansion Input RXINeg : IN std_logic := 'X'; -- Read Expansion Input EFNeg : OUT std_logic := 'U'; -- Empty Flag PAENeg : OUT std_logic := 'U'; -- Programmable Almost Empty Flag PAFNeg : OUT std_logic := 'U'; -- Programmable Almost Full Flag FFNeg : OUT std_logic := 'U'; -- Full Flag WXOHFNeg : OUT std_logic := 'U'; -- Write Expansion Out/ -- Half-Full Flag RXONeg : OUT std_logic := 'U'; -- Read Expansion Out Q0 : OUT std_logic := 'U'; -- Data Output Bus Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q7 : OUT std_logic := 'U'; Q8 : OUT std_logic := 'U'; Q9 : OUT std_logic := 'U'; Q10 : OUT std_logic := 'U'; Q11 : OUT std_logic := 'U'; Q12 : OUT std_logic := 'U'; Q13 : OUT std_logic := 'U'; Q14 : OUT std_logic := 'U'; Q15 : OUT std_logic := 'U'; Q16 : OUT std_logic := 'U'; Q17 : OUT std_logic := 'U' ); ATTRIBUTE VITAL_LEVEL0 OF IDT72805 : ENTITY IS TRUE;END IDT72805;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral OF IDT72805 IS ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE; -- RAM definition CONSTANT RAMWordLength : positive := 18; -- number of bits in RAM word CONSTANT AddrBitNum : positive := 8; -- number of bits in RAM address CONSTANT RAMSize : positive := 2**AddrBitNum; CONSTANT HalfSize : positive := RAMSize/2; CONSTANT OffsetLength : positive := 10; -- number of bits in Offset Reg CONSTANT Default_Val : natural := 31; -- for Offset Reg after Reset CONSTANT partID : String := "IDT72805"; SUBTYPE RAM_Word IS Std_Logic_Vector (RAMWordLength-1 DOWNTO 0); TYPE RAM_Array IS ARRAY (RAMSize-1 DOWNTO 0) OF RAM_Word; SUBTYPE Point IS Std_Logic_Vector (AddrBitNum-1 DOWNTO 0); --SUBTYPE Ex_Point IS Std_Logic_Vector (AddrBitNum DOWNTO 0); -- delayed inputs SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL D8_ipd : std_ulogic := 'X'; SIGNAL D9_ipd : std_ulogic := 'X'; SIGNAL D10_ipd : std_ulogic := 'X'; SIGNAL D11_ipd : std_ulogic := 'X'; SIGNAL D12_ipd : std_ulogic := 'X'; SIGNAL D13_ipd : std_ulogic := 'X'; SIGNAL D14_ipd : std_ulogic := 'X'; SIGNAL D15_ipd : std_ulogic := 'X'; SIGNAL D16_ipd : std_ulogic := 'X'; SIGNAL D17_ipd : std_ulogic := 'X'; SIGNAL RSNeg_ipd : std_ulogic := 'X'; SIGNAL WCLK_ipd : std_ulogic := 'X'; SIGNAL WENNeg_ipd : std_ulogic := 'X'; SIGNAL RCLK_ipd : std_ulogic := 'X'; SIGNAL RENNeg_ipd : std_ulogic := 'X'; SIGNAL OENeg_ipd : std_ulogic := 'X'; SIGNAL LDNeg_ipd : std_ulogic := 'X'; SIGNAL WXINeg_ipd : std_ulogic := 'X'; SIGNAL RXINeg_ipd : std_ulogic := 'X'; -- internal signals SIGNAL RAM : RAM_Array ; SIGNAL Write_Pointerint, WritePnt_Sumint : Natural; SIGNAL Read_Pointerint : Natural ; SIGNAL Write_PRint,Read_PRint: Point; SIGNAL Wr_Pnt_Delint: Point; SIGNAL PAE_Offset_Regint,PAF_Offset_Regint: std_logic_vector( OffsetLength-1 Downto 0); SIGNAL Zerosint : std_logic_vector(RAMWordLength-OffsetLength-1 Downto 0); SIGNAL Fullint,Emptyint,HFint,FF_Delint : std_logic; SIGNAL Almost_Fullint,Almost_Emptyint : std_logic; SIGNAL AlmEmp_Setint,AlmEmp_Resint : std_logic; SIGNAL AlmFull_Setint,AlmFull_Resint : std_logic; SIGNAL HlfFull_Setint,HlfFull_Resint : std_logic; SIGNAL Read_Flint,Write_Flint : std_logic; SIGNAL Write_Enableint,Read_Enableint,Read_En_Delint : std_logic; SIGNAL Input_Regint : RAM_Word; SIGNAL Wr_Offset_Pntint,Rd_Offset_Pntint : std_logic; SIGNAL WrP_mn_RdPint,RdP_mn_WrPint : integer; SIGNAL WrP_GE_RdPint: std_logic; SIGNAL Depth_Expanint: std_logic; SIGNAL WXOint: std_logic; SIGNAL Output_Regint,Data_Outint : RAM_Word; SIGNAL WXO_Tg1int,WXO_Tg2int: std_logic; SIGNAL RXO_Tg1int, RXO_Tg2int : std_logic; SIGNAL Wr_RAM_Onint,Rd_RAM_Onint: std_logic; SIGNAL Wr_RAM_Delint : std_logic; SIGNAL Wr_Ofs_Onint,Rd_Ofs_Onint: std_logic; SIGNAL No_Expanint : std_logic; SIGNAL OpenIn, OpenOut : std_logic; -- Additional Delayed Signals SIGNAL Write_PRint_DEL, Read_PRint_DEL: Point; SIGNAL Read_Flint_DEL, Write_Flint_DEL: std_logic;BEGIN---------------------------------------------------------------------------------- Dummy instances for exporting tSKEW vals from SDF file-- using DEVICE construct-------------------------------------------------------------------------------- SKEW1 : VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));---------------------------------------------------------------------------------- Wire Delays ----------------------------------------------------------------------------------WireDelay : BLOCKBEGIN w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0 ); w_2: VitalWireDelay (D1_ipd, D1, tipd_D1 ); w_3: VitalWireDelay (D2_ipd, D2, tipd_D2 ); w_4: VitalWireDelay (D3_ipd, D3, tipd_D3 ); w_5: VitalWireDelay (D4_ipd, D4, tipd_D4 ); w_6: VitalWireDelay (D5_ipd, D5, tipd_D5 ); w_7: VitalWireDelay (D6_ipd, D6, tipd_D6 ); w_8: VitalWireDelay (D7_ipd, D7, tipd_D7 ); w_9: VitalWireDelay (D8_ipd, D8, tipd_D8 ); w_10: VitalWireDelay (D9_ipd, D9, tipd_D9 ); w_11 : VitalWireDelay (D10_ipd, D10, tipd_D10 ); w_12: VitalWireDelay (D11_ipd, D11, tipd_D11 ); w_13: VitalWireDelay (D12_ipd, D12, tipd_D12 ); w_14: VitalWireDelay (D13_ipd, D13, tipd_D13 ); w_15: VitalWireDelay (D14_ipd, D14, tipd_D14 ); w_16: VitalWireDelay (D15_ipd, D15, tipd_D15 ); w_17: VitalWireDelay (D16_ipd, D16, tipd_D16 ); w_18: VitalWireDelay (D17_ipd, D17, tipd_D17 ); w_19: VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg ); w_20: VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK ); w_21 : VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg ); w_22: VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK ); w_23: VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg ); w_24: VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg ); w_25: VitalWireDelay (LDNeg_ipd, LDNeg, tipd_LDNeg ); w_26: VitalWireDelay (WXINeg_ipd, WXINeg, tipd_WXINeg ); w_27: VitalWireDelay (RXINeg_ipd, RXINeg, tipd_RXINeg );END BLOCK;---------------------------------------------------------------------------------- Main Behavior Block ----------------------------------------------------------------------------------VITALBehavior: BLOCK PORT ( D : IN RAM_Word := (OTHERS => 'X'); RSNeg : IN std_logic := 'X' ; WCLK : IN std_logic := 'X' ;⌨️ 快捷键说明
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