idt72265.vhd

VHDL的ram和fifo model code 包含众多的厂家

                             IF WRITEPtrint = FIFOSize - 1 THEN
                                 WRITEPtrint <= 0;
                             ELSE WRITEPtrint <= WRITEPtrint + 1;
                             END IF;

                             FWPassedint     <= '0';
                             OutputLoadedint <= '0';

                          END IF;

                    END IF;

                    InputLoadedint <= '0';

            ELSIF FIFOOperableint THEN              -- I/O logic

               IF (WCLK'event AND WCLK = '1') THEN  -- synch by WCLK

                  IF WRITEint = '1' AND WRITEPossibleint = '1' THEN    -- WRITE

                     InputRegint    <= D;        -- load data in input Reg
                     InputLoadedint <= '1';

                  ELSIF PLOADint = '1' AND PLOADPossibleint = '1' THEN -- PLOAD

                        IF WrOffsRegPtrint = 0 THEN

                           OffsetRegint(OffsLen/2-1 DOWNTO 0) <=
                           D(OffsLen/2-1 DOWNTO 0);

                           WrOffsRegPtrint <= 1;  -- Empty offs loaded

                        ELSIF WrOffsRegPtrint = 1 THEN

                           OffsetRegint(OffsLen-1 DOWNTO OffsLen/2) <=
                           D(OffsLen/2-1 DOWNTO 0);

                           WrOffsRegPtrint <= 0;  -- Full offset loaded

                        END IF;

                  ELSIF SLOADint = '1' AND SLOADPossibleint = '1' THEN -- SLOAD

                        OffsetRegint(WrOffsRegPtrint) <= FWFTSI; -- load a bit

                        IF WrOffsRegPtrint = OffsLen-1 THEN -- MSB is reached
                           WrOffsRegPtrint <= 0;            -- reset to LSB
                        ELSE
                           WrOffsRegPtrint <= WrOffsRegPtrint + 1;-- advance ptr
                        END IF;

                  ELSE
                        NULL;
                  END IF;

               END IF;

               IF (RCLK'event AND RCLK = '1') THEN     -- synch by RCLK

                  IF RETRint = '1' AND RETRPossibleint = '1' THEN    -- RETARNS

                     -- retransmit setup

                     RTSCompletedint <= '0';

                     IF Frequencyint = '0' THEN        -- RCLK is faster or =
                        Tf := tperiod_RCLK_posedge;    -- WCLK
                     ELSIF Frequencyint = '1' THEN     -- WCLK is faster
                        Tf := tperiod_WCLK_posedge;
                     END IF;

                     IF OpModeint = '0' THEN           -- Standard Mode

                        READPtrint      <= 0;          -- initialize read ptr
                        RTSCompletedint <= '1'
                                           AFTER 14*Tf+3*tperiod_RCLK_posedge;

                     ELSIF OpModeint = '1' THEN        -- FWFT mode

                        READPtrint      <= 0,          -- initialize read ptr
                                           1 AFTER 14*Tf+4*tperiod_RCLK_posedge;
                        RTSCompletedint <= '1'
                                           AFTER 14*Tf+4*tperiod_RCLK_posedge;
                        OutputRegint    <= FIFOMemory(0);

                     END IF;

                  ELSIF READint = '1' AND READPossibleint = '1' THEN -- READ

                        -- reading memory to output register

                        OutputRegint    <= FIFOMemory(READPtrint);
                        OutputLoadedint <= '1';
                        StillNoReadint  <= '0'; -- reset still no read flag

                        -- modification of the READ pointer

                        IF READPtrint = FIFOSize - 1 THEN
                           READPtrint <= 0;
                        ELSE READPtrint <= READPtrint + 1;
                        END IF;

                  ELSIF PREADint = '1' AND PREADPossibleint = '1' THEN -- PREAD

                        -- parallel read from PAF/PAE offsets register

                        IF RdOffsRegPtrint = 0 THEN

                           OutputRegint <=            -- load PAE offs
                           to_slv(to_nat(OffsetRegint(OffsLen/2-1 DOWNTO 0)),
                                  FIFOWordLength);

                           OutputLoadedint <= '1';
                           RdOffsRegPtrint <= 1;      -- jump to full offs part

                        ELSIF RdOffsRegPtrint = 1 THEN

                           OutputRegint <=            -- load PAF offs
                           to_slv(to_nat(OffsetRegint(OffsLen-1 DOWNTO
                                                      OffsLen/2)),
                                  FIFOWordLength);

                           OutputLoadedint <= '1';
                           RdOffsRegPtrint <= 0;  -- jump to empty offset part

                        END IF;
                  ELSE
                        OutputLoadedint <= '0';
                  END IF;

               ELSE OutputLoadedint <= '0';

               END IF;

            END IF;

        END PROCESS FIFOArrayIO;

        ------------------------------------------------------------------------
        -- Counting number of words in FIFO                                   --
        ------------------------------------------------------------------------

        WordCounter: PROCESS (WRITEPtrint, READPtrint)
        BEGIN

            IF    WRITEPtrint > READPtrint            -- no overrun
            THEN  WordCountint <= WRITEPtrint - READPtrint;
                  FWPassed2int <= '1';

            ELSIF WRITEPtrint < READPtrint            -- overrun
            THEN  WordCountint <= (FIFOArray'high - READPtrint + 1) +
                                  (WRITEPtrint - FIFOArray'low);
                  FWPassed2int <= '1';

            ELSIF (WRITEPtrint = READPtrint)  AND
                  WordCountint = FIFOSize - 1         -- WRptr've caught RDptr
            THEN  WordCountint <= FIFOSize;
                  FWPassed2int <= '1';

            ELSIF (WRITEPtrint = READPtrint)  AND
                  WordCountint = 1                    -- RDptr've caught WRptr
            THEN  WordCountint <= 0;
                  FWPassed2int <= '0';

            END IF;

        END PROCESS WordCounter;


        ------------------------------------------------------------------------
        -- Detection of the actual tSKEW vals                                --
        ------------------------------------------------------------------------

        SkewDetector: PROCESS(RCLK, WCLK)

            VARIABLE tRCLKposedge : Time := 0 ns;
            VARIABLE tWCLKposedge : Time := 0 ns;

        BEGIN

            IF RCLK'event AND RCLK = '1'
            THEN tRCLKposedge := Now;
                 tSKEW_WCLK_RCLK <= Now - tWCLKposedge;
            END IF;

            IF WCLK'event AND WCLK = '1'
            THEN tWCLKposedge := Now;
                 tSKEW_RCLK_WCLK <= Now - tRCLKposedge;
            END IF;

        END PROCESS SkewDetector;

        ------------------------------------------------------------------------
        -- Flag Logic                                                         --
        ------------------------------------------------------------------------
        ------------------------------------------------------------------------
        -- EFOR & PAE flags update                                            --
        ------------------------------------------------------------------------

        EFORUpdate: PROCESS (MRSNeg, PRSNEg, RCLK, RTSCompletedint)

            VARIABLE Tf    : Time;
            VARIABLE Ahead : Natural RANGE 0 TO 1;

        BEGIN

           IF MRSNeg = '0' THEN    -- master reset

              PAENeg_zd  <= '0';
              EFORNeg_zd <= FWFTSI;

           ELSIF PRSNeg = '0' THEN -- partial reset

              PAENeg_zd  <= '0';
              EFORNeg_zd <= OpMOdeint;

           ELSIF RTSCompletedint'event AND RTSCompletedint = '0' THEN

                  IF OpModeint = '0' THEN            -- in standard mode
                     EFORNeg_zd <= '1';
                  ELSIF OpModeInt = '1' THEN         -- in FWFT mode
                     EFORNeg_zd <= '0';
                  END IF;

           ELSE   -- RCLK'event is assumed

              IF (RCLK = '1')      AND
                 (FIFOOperableint) AND
                 (RETRint = '1'    AND RETRPossibleint = '1') THEN

                  -- retransmit setup

                  IF Frequencyint = '0' THEN     -- RCLK is faster or eq to WCLK
                     Tf := tperiod_RCLK_posedge;
                  ELSIF Frequencyint = '1' THEN  -- WCLK is faster
                     Tf := tperiod_WCLK_posedge;
                  END IF;

                  IF OpModeint = '0' THEN            -- in standard mode
                     EFORNeg_zd <= '0';
                  ELSIF OpModeInt = '1' THEN         -- in FWFT mode
                     EFORNeg_zd <= '1';
                  END IF;

              ELSIF RCLK = '1'      AND
                    FIFOOperableint AND
                    FIFORStateint /= RESETUP  THEN

                    IF  RENNEg = '0'
                    THEN
                        Ahead := 1;    -- look ahead during read cycle
                    ELSE
                        Ahead := 0;
                    END IF;

                    IF (WordCountint = 0) OR
                       (WordCountint > 0 AND WordCountint-Ahead = 0) THEN
                       EFORNeg_zd <= OpModeint;
                    ELSE
                       EFORNeg_zd <= NOT OpModeint;
                    END IF;

                    IF (WordCountint = 0) OR
                      (WordCountint > 0 AND WordCountint-Ahead <= EmptyOffsetint)
                    THEN   -- assertion of the PAE flag
                       IF PAEValidint = '1'
                       THEN
                          PAENeg_zd <= '0';
                       ELSE
                          PAENeg_zd <= 'X';
                       END IF;
                    ELSE   -- deassertion of the PAE flag
                      IF (tSKEW_WCLK_RCLK >= tSKEW2)
                      THEN
                         IF (PAEValidint = '1')
                         THEN
                            PAENeg_zd <= '1' AFTER (tRCLK);
                         ELSE
                            PAENeg_zd <= 'X' AFTER (tRCLK);
                         END IF;
                      ELSE
                         IF (PAEValidint = '1')
                         THEN
                            PAENeg_zd <= '1' AFTER (tRCLK*2);
                         ELSE
                            PAENeg_zd <= 'X' AFTER (tRCLK*2);
                         END IF;
                      END IF;
                    END IF;
              END IF;
           END IF;

        END PROCESS EFORUpdate;


        ------------------------------------------------------------------------
        -- HF flag update                                                     --
        ------------------------------------------------------------------------

        HFUpdate: PROCESS (MRSNeg, PRSNEg, RCLK, WCLK)

            VARIABLE Ahead : Natural RANGE 0 TO 1;

        BEGIN

           IF (MRSNeg = '0') OR     -- master reset
              (PRSNeg = '0') THEN   -- partial reset

              HFNeg_zd <= '1';

           ELSIF (FIFOOperableint)          AND
                 (FIFORStateint /= RESE