📄 idt72265.vhd
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IF WCLK'event THEN VitalPeriodPulseCheck ( TestSignal => WCLK, TestSignalName => "WCLK", Period => tperiod_WCLK_posedge, PulseWidthHigh => tpw_WCLK_posedge, PulseWidthLow => tpw_WCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WCLK); END IF; --2 RCLK pulse (low & high) width and period check -- (tRCLK, tRCLKH, tRCLKL) IF RCLK'event THEN VitalPeriodPulseCheck ( TestSignal => RCLK, TestSignalName => "RCLK", Period => tperiod_RCLK_posedge, PulseWidthHigh => tpw_RCLK_posedge, PulseWidthLow => tpw_RCLK_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_RCLK); END IF; --3 MRSNeg low pulse width check (tRS) IF MRSNeg'event THEN VitalPeriodPulseCheck ( TestSignal => MRSNeg, TestSignalName => "MRSNEg", PulseWidthLow => tpw_MRSNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_MRSNeg); END IF; --4 PRSNeg low pulse width check (tRS) IF PRSNeg'event THEN VitalPeriodPulseCheck ( TestSignal => PRSNeg, TestSignalName => "PRSNEg", PulseWidthLow => tpw_MRSNeg_negedge, CheckEnabled => TRUE, HeaderMsg => InstancePath & partID, PeriodData => PD_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_PRSNeg); END IF; IF FIFOWStateint /= MRS AND FIFOWStateint /= PRS AND FIFORStateint /= MRS AND FIFORStateint /= PRS THEN --(exclude 5-8 if reset) --5 D/WCLK setup/hold time check (tDS, tDH) IF D'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => D, TestSignalName => "D", RefSignal => WCLK, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK_noedge_posedge, SetupLow => tsetup_D0_WCLK_noedge_posedge, HoldHigh => thold_D0_WCLK_noedge_posedge, HoldLow => thold_D0_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_D0_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D0_WCLK); END IF; --6 WENNeg/WCLK setup/hold time check (tENS, tENH) IF WENNeg'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNEg, TestSignalName => "WENNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK); END IF; -- SENNeg/WCLK setup/hold time check (tENS, tENH) IF SENNeg'event OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNEg, TestSignalName => "SENNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_WCLK); END IF; --7 RENNeg/RCLK setup/hold time check (tENS, tENH) IF RENNeg'event OR (RCLK'event AND RCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNEg, TestSignalName => "RENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK); END IF; --8 LDNeg/WCLK setup/hold time check (tLDS/tLDH) IF LDNeg'event OR ((WCLK'event AND WCLK = '1') AND (WENNeg = '0' OR SENNeg = '0')) THEN VitalSetupHoldCheck ( TestSignal => LDNEg, TestSignalName => "LDNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_LDNeg_WCLK_noedge_posedge, HoldHigh => thold_LDNeg_WCLK_noedge_posedge, CheckEnabled => (LDNeg'event AND (WENNegOnWCLKint = '0' OR SENNegOnWCLKint = '0')) OR ((WCLK'event AND WCLK = '1') AND (WENNeg = '0' OR SENNeg = '0')), RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_WCLK); END IF; --8 LDNeg/RCLK setup/hold time check (tLDS/tLDH) IF LDNeg'event OR ((RCLK'event AND RCLK = '1') AND (RENNeg = '0')) THEN VitalSetupHoldCheck ( TestSignal => LDNEg, TestSignalName => "LDNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_LDNeg_WCLK_noedge_posedge, HoldHigh => thold_LDNeg_WCLK_noedge_posedge, CheckEnabled => (LDNeg'event AND RENNegOnRCLKint = '0') OR ((RCLK'event AND RCLK = '1') AND (RENNeg = '0')), RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RCLK); END IF; END IF; --9 RENNeg/MRSNeg setup time check (tRSS) IF RENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNEg, TestSignalName => "RENNeg", RefSignal => MRSNEg, RefSignalName => "MRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg); END IF; --10 WENNeg/MRSNeg setup time check (tRSS) IF WENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNEg, TestSignalName => "WENNeg", RefSignal => MRSNEg, RefSignalName => "MRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg); END IF; --11 LDNeg/MRSNeg setup time check (tRSS) IF LDNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => LDNEg, TestSignalName => "LDNeg", RefSignal => MRSNEg, RefSignalName => "MRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, SetupLow => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_MRSNeg); END IF; --12 RTNeg/MRSNeg setup time check (tRSS) IF RTNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNEg, TestSignalName => "RTNeg", RefSignal => MRSNEg, RefSignalName => "MRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_MRSNeg); END IF; --13 SENNeg/MRSNeg setup time check (tRSS) IF SENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNEg, TestSignalName => "SENNeg", RefSignal => MRSNEg, RefSignalName => "MRSNEg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg); END IF; --14 RENNeg/PRSNeg setup time check (tRSS)⌨️ 快捷键说明
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