idt72265.vhd

VHDL的ram和fifo model code 包含众多的厂家

    SIGNAL WordCountint    : Natural RANGE 0 TO FIFOSize; -- FIFO word counter
    SIGNAL WENIgnoredint   : std_ulogic := 'X';    -- WEN is ignored when '1'
    SIGNAL RENIgnoredint   : std_ulogic := 'X';    -- REN is ignored when '1'
    SIGNAL FWPassedint     : std_ulogic := 'X';    -- first word passed flag
    SIGNAL FWPassed1int    : std_ulogic := 'X';    -- first word passed flag
    SIGNAL FWPassed2int    : std_ulogic := 'X';    -- first word passed flag
    SIGNAL PLOADint        : std_ulogic := 'X';    -- parallel load detected
    SIGNAL PREADint        : std_ulogic := 'X';    -- parallel read detected
    SIGNAL SLOADint        : std_ulogic := 'X';    -- serial load detected
    SIGNAL WRITEint        : std_ulogic := 'X';    -- write cycle detected
    SIGNAL READint         : std_ulogic := 'X';    -- read  cycle detected
    SIGNAL RETRint         : std_ulogic := 'X';    -- retransmit setup detected
    SIGNAL READPossibleint : std_ulogic := 'X';    -- READ possible flag
    SIGNAL WRITEPossibleint: std_ulogic := 'X';    -- WRITE possible flag
    SIGNAL RETRPossibleint : std_ulogic := 'X';    -- RETRANSMIT possible flag
    SIGNAL PLOADPossibleint: std_ulogic := 'X';    -- PARALLEL load possible flg
    SIGNAL PREADPossibleint: std_ulogic := 'X';    -- PARALLEL read possible flg
    SIGNAL SLOADPossibleint: std_ulogic := 'X';    -- SERIAL load possible flag
    SIGNAL InputLoadedint  : std_ulogic := 'X';    -- input reg loaded flag
    SIGNAL OutputLoadedint : std_ulogic := 'X';    -- output reg loaded flag
    SIGNAL ParaLoadingint  : std_ulogic := 'X';    -- parallel loading enabled
    SIGNAL SeriLoadingint  : std_ulogic := 'X';    -- serial loading enabled
    SIGNAL OffsetRegint    : std_logic_vector(OffsLen-1 DOWNTO 0)
                             := (OTHERS => 'X');   -- a register for loading
                                                   -- full and empty offsets
    SIGNAL RdOffsRegPtrint : Natural RANGE 0 TO OffsLen-1; -- read offs reg ptr
    SIGNAL WrOffsRegPtrint : Natural RANGE 0 TO OffsLen-1; -- write offs reg ptr
    SIGNAL StillNoReadint  : std_ulogic := 'X';    -- '1' - no read since RS
    SIGNAL PAEValidint     : std_ulogic := 'X';    -- PAE is valid when '1'
    SIGNAL PAFValidint     : std_ulogic := 'X';    -- PAF is valid when '1'
    SIGNAL RTSCompletedint : std_ulogic := 'X';    -- Retransmit setup completed

   SIGNAL WENNegOnWCLKint, SENNegOnWCLKint, RENNegOnRCLKint : std_ulogic;
   
    -- SKEW stuff (see also generics list)

    ALIAS  tSKEW1          : VitalDelayType IS tdevice_SKEW1;
    ALIAS  tSKEW2          : VitalDelayType IS tdevice_SKEW2;
    SIGNAL tSKEW_WCLK_RCLK : Time := 0 ns;         -- actual /WCLK/RCLK skew time
    SIGNAL tSKEW_RCLK_WCLK : Time := 0 ns;         -- actual /RCLK/WCLK skew time
    SIGNAL OpenIn, OpenOut : std_logic;
    ALIAS  tRCLK           : VitalDelayType IS tperiod_RCLK_posedge;
    ALIAS  tWCLK           : VitalDelayType IS tperiod_WCLK_posedge;

BEGIN  -- architecture body

    -----------------------------------------------------------------------------
    -- Dummy instances for exporting tSKEW vals from SDF file
    -- using DEVICE construct
    -----------------------------------------------------------------------------

    SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1));

    SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));


    ----------------------------------------------------------------------------
    -- Wire Delays                                                            --
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1:  VitalWireDelay (D0_ipd    , D0    ,  tipd_D0    );
        w_2:  VitalWireDelay (D1_ipd    , D1    ,  tipd_D1    );
        w_3:  VitalWireDelay (D2_ipd    , D2    ,  tipd_D2    );
        w_4:  VitalWireDelay (D3_ipd    , D3    ,  tipd_D3    );
        w_5:  VitalWireDelay (D4_ipd    , D4    ,  tipd_D4    );
        w_6:  VitalWireDelay (D5_ipd    , D5    ,  tipd_D5    );
        w_7:  VitalWireDelay (D6_ipd    , D6    ,  tipd_D6    );
        w_8:  VitalWireDelay (D7_ipd    , D7    ,  tipd_D7    );
        w_9:  VitalWireDelay (D8_ipd    , D8    ,  tipd_D8    );
        w_10: VitalWireDelay (D9_ipd    , D9    ,  tipd_D9    );
        w_11: VitalWireDelay (D10_ipd   , D10   ,  tipd_D10   );
        w_12: VitalWireDelay (D11_ipd   , D11   ,  tipd_D11   );
        w_13: VitalWireDelay (D12_ipd   , D12   ,  tipd_D12   );
        w_14: VitalWireDelay (D13_ipd   , D13   ,  tipd_D13   );
        w_15: VitalWireDelay (D14_ipd   , D14   ,  tipd_D14   );
        w_16: VitalWireDelay (D15_ipd   , D15   ,  tipd_D15   );
        w_17: VitalWireDelay (D16_ipd   , D16   ,  tipd_D16   );
        w_18: VitalWireDelay (D17_ipd   , D17   ,  tipd_D17   );
        w_19: VitalWireDelay (MRSNeg_ipd, MRSNeg,  tipd_MRSNeg);
        w_20: VitalWireDelay (PRSNeg_ipd, PRSNeg,  tipd_PRSNeg);
        w_21: VitalWireDelay (RTNeg_ipd , RTNeg ,  tipd_RTNeg );
        w_22: VitalWireDelay (FWFTSI_ipd, FWFTSI,  tipd_FWFTSI);
        w_23: VitalWireDelay (WCLK_ipd  , WCLK  ,  tipd_WCLK  );
        w_24: VitalWireDelay (WENNeg_ipd, WENNeg,  tipd_WENNeg);
        w_25: VitalWireDelay (RCLK_ipd  , RCLK  ,  tipd_RCLK  );
        w_26: VitalWireDelay (RENNeg_ipd, RENNeg,  tipd_RENNeg);
        w_27: VitalWireDelay (OENeg_ipd , OENeg ,  tipd_OENeg );
        w_28: VitalWireDelay (SENNeg_ipd, SENNeg,  tipd_SENNeg);
        w_29: VitalWireDelay (LDNeg_ipd , LDNeg ,  tipd_LDNeg );
        w_30: VitalWireDelay (FS_ipd    , FS    ,  tipd_FS    );

    END BLOCK WireDelay;

    ----------------------------------------------------------------------------
    -- Main Behavior Block                                                    --
    ----------------------------------------------------------------------------

    VitalBehavior: BLOCK

        PORT (
            D        : IN  std_logic_vector(FIFOWordLength-1 DOWNTO 0) :=
                                           (OTHERS => 'X');
            MRSNeg   : IN  std_logic := 'X';
            PRSNeg   : IN  std_logic := 'X';
            RTNeg    : IN  std_logic := 'X';
            FWFTSI   : IN  std_logic := 'X';
            WCLK     : IN  std_logic := 'X';
            WENNeg   : IN  std_logic := 'X';
            RCLK     : IN  std_logic := 'X';
            RENNeg   : IN  std_logic := 'X';
            OENeg    : IN  std_logic := 'X';
            SENNeg   : IN  std_logic := 'X';
            LDNeg    : IN  std_logic := 'X';
            FS       : IN  std_logic := 'X';
            FFIRNeg  : OUT std_logic := 'U';
            EFORNeg  : OUT std_logic := 'U';
            PAFNeg   : OUT std_logic := 'U';
            PAENeg   : OUT std_logic := 'U';
            HFNeg    : OUT std_logic := 'U';
            Q        : OUT std_logic_vector(FIFOWordLength-1 DOWNTO 0) :=
                                           (OTHERS => 'U'));

        PORT MAP (
            D(0)    => D0_ipd,
            D(1)    => D1_ipd,
            D(2)    => D2_ipd,
            D(3)    => D3_ipd,
            D(4)    => D4_ipd,
            D(5)    => D5_ipd,
            D(6)    => D6_ipd,
            D(7)    => D7_ipd,
            D(8)    => D8_ipd,
            D(9)    => D9_ipd,
            D(10)   => D10_ipd,
            D(11)   => D11_ipd,
            D(12)   => D12_ipd,
            D(13)   => D13_ipd,
            D(14)   => D14_ipd,
            D(15)   => D15_ipd,
            D(16)   => D16_ipd,
            D(17)   => D17_ipd,
            MRSNeg  => MRSNeg_ipd,
            PRSNeg  => PRSNeg_ipd,
            RTNeg   => RTNeg_ipd,
            FWFTSI  => FWFTSI_ipd,
            WCLK    => WCLK_ipd,
            WENNeg  => WENNeg_ipd,
            RCLK    => RCLK_ipd,
            RENNeg  => RENNeg_ipd,
            OENeg   => OENeg_ipd,
            SENNeg  => SENNeg_ipd,
            LDNeg   => LDNeg_ipd,
            FS      => FS_ipd,
            FFIRNeg => FFIRNeg,
            EFORNeg => EFORNeg,
            PAFNeg  => PAFNeg,
            PAENeg  => PAENeg,
            HFNeg   => HFNeg,
            Q(0)    => Q0,
            Q(1)    => Q1,
            Q(2)    => Q2,
            Q(3)    => Q3,
            Q(4)    => Q4,
            Q(5)    => Q5,
            Q(6)    => Q6,
            Q(7)    => Q7,
            Q(8)    => Q8,
            Q(9)    => Q9,
            Q(10)   => Q10,
            Q(11)   => Q11,
            Q(12)   => Q12,
            Q(13)   => Q13,
            Q(14)   => Q14,
            Q(15)   => Q15,
            Q(16)   => Q16,
            Q(17)   => Q17);

    BEGIN -- VitalBehavior block

        ------------------------------------------------------------------------
        -- Timing Check Section                                               --
        ------------------------------------------------------------------------
        TimingChecks: PROCESS (D,      MRSNeg, PRSNeg, RTNeg,  FWFTSI, WCLK,
                               WENNeg, RCLK,   RENNeg, OENeg,  SENNeg, LDNeg,
                               WENNegOnWCLKint, SENNegOnWCLKint, RENNegOnRCLKint)

            -- Timing Check Variables

            -- Pulse Width & Period Check Variables

            VARIABLE Pviol_WCLK          : X01 := '0';
            VARIABLE PD_WCLK             : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            VARIABLE Pviol_RCLK          : X01 := '0';
            VARIABLE PD_RCLK             : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            VARIABLE Pviol_MRSNeg        : X01 := '0';
            VARIABLE PD_MRSNeg           : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            VARIABLE Pviol_PRSNeg        : X01 := '0';
            VARIABLE PD_PRSNeg           : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            -- Setup/Hold Check Variables

            VARIABLE Tviol_D0_WCLK       : X01 := '0';
            VARIABLE TD_D0_WCLK          : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_WCLK   : X01 := '0';
            VARIABLE TD_WENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_WCLK   : X01 := '0';
            VARIABLE TD_SENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_RCLK   : X01 := '0';
            VARIABLE TD_RENNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_WCLK    : X01 := '0';
            VARIABLE TD_LDNeg_WCLK       : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_RCLK    : X01 := '0';
            VARIABLE TD_LDNeg_RCLK       : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_MRSNeg  : X01 := '0';
            VARIABLE TD_LDNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_MRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_PRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_PRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_FWFTSI_MRSNeg : X01 := '0';
            VARIABLE TD_FWFTSI_MRSNeg    : VitalTimingDataType;

            -- Recovery Check Variables

            VARIABLE Rviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE RD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE RD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_LDNeg_MRSNeg  : X01 := '0';
            VARIABLE RD_LDNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Rviol_FWFTSI_MRSNeg : X01 := '0';
            VARIABLE RD_FWFTSI_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE RD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE RD_RENNeg_PRSNeg    : VitalTimingDataType;

            -- Violation variable (used to OR all individual violations)

            VARIABLE Violation           : X01 := '0';

        BEGIN  -- timing checks process

            IF  (TimingChecksOn) THEN

              Pviol_WCLK          := '0';
              Pviol_RCLK          := '0';
              Pviol_MRSNeg        := '0';
              Pviol_PRSNeg        := '0';
              Tviol_D0_WCLK       := '0';
              Tviol_WENNeg_WCLK   := '0';
              Tviol_SENNeg_WCLK   := '0';
              Tviol_RENNeg_RCLK   := '0';
              Tviol_LDNeg_WCLK    := '0';
              Tviol_WENNeg_MRSNeg := '0';
              Tviol_RENNeg_MRSNeg := '0';
              Tviol_LDNeg_MRSNeg  := '0';
              Tviol_RTNeg_MRSNeg  := '0';
              Tviol_SENNeg_MRSNeg := '0';
              Tviol_WENNeg_PRSNeg := '0';
              Tviol_RENNeg_PRSNeg := '0';
              Tviol_RTNeg_PRSNeg  := '0';
              Tviol_SENNeg_PRSNeg := '0';
              Tviol_FWFTSI_MRSNeg := '0';
              Rviol_WENNeg_MRSNeg := '0';
              Rviol_RENNeg_MRSNeg := '0';
              Rviol_LDNeg_MRSNeg  := '0';
              Rviol_FWFTSI_MRSNeg := '0';
              Rviol_WENNeg_PRSNeg := '0';
              Rviol_RENNeg_PRSNeg := '0';

              --1 WCLK pulse (low & high) width and period check
              --  (tWCLK, tWCLKH, tWCLKL)