idt72105.vhd

VHDL的ram和fifo model code 包含众多的厂家

                    END IF;
                ELSIF Count < Half THEN
                    FFNeg_zd := '1';
                    HFNeg_zd := '1';
                    IF mode = single THEN
                        RSOX_zd := '1';
                    END IF;
                ELSIF Count < Aeh THEN
                    HFNeg_zd := '0';
                    FFNeg_zd := '0';
                    IF mode = single THEN
                        RSOX_zd := '1';
                    END IF;
                ELSIF Count < TotalLOC THEN
                    HFNeg_zd := '0';
                    FFNeg_zd := '1';
                    IF mode = single THEN
                        RSOX_zd := '0';
                    END IF;
                ELSE
                    FFNeg_zd := '0';
                    HFNeg_zd := '0';
                    IF mode = single THEN
                        RSOX_zd := '0';
                    ELSE 
                        RSOX_zd := '1';                        
                    END IF;
                    wr_inhibit := true;
                END IF;
            END IF;
    ELSIF rising_edge(WNeg) THEN
        IF EFNeg_zd = '0' AND SOCPIn = '0' THEN
            EF_pzd := '1';
        END IF;        
    END IF;

    -- Serial out --

    IF rising_edge(SOCPIn) AND EFNeg_zd = '1' AND reset_done THEN 
        IF rd_stat = act THEN            
            IF MemData(RDPoint) >= 0 THEN
                DataDrive := to_slv(MemData(RDPoint), DataWidth);
            ELSE
                DataDrive := (OTHERS=>'X');
            END IF;
            IF FLNegIn='0' THEN     
                DataDriveOut := DataDrive(BitPoint); -- DIR='1' LSB out first
            ELSE 
                -- DIR='0' MSB out first
                DataDriveOut := DataDrive(HiDbit - BitPoint);
            END IF;
            IF BitPoint = HiDbit THEN
                BitPoint := 0;
                IF RDPoint = TotalLoc THEN
                    RDPoint := 0;
                ELSE
                    RDPoint := RDPoint + 1;
                END IF;
                    Count := Count - 1;
                IF Count = 0 THEN
                     EFNeg_zd := '0';
                     IF mode /= single THEN
                         RSOX_zd := '1';
                         rd_stat := inact;
                      END IF;
                END IF;
            ELSE
                BitPoint := BitPoint + 1;
            END IF;
            IF Count < Ael THEN
               FFNeg_zd := '1';
               HFNeg_zd := '1';
               IF mode = single THEN
                   RSOX_zd := '0';
               END IF;
            ELSIF Count < Half THEN
               FFNeg_zd := '1';
               HFNeg_zd := '1';
               IF mode = single THEN
                   RSOX_zd := '1';
               END IF;
            ELSIF Count < Aeh THEN
               FFNeg_zd := '1';
               HFNeg_zd := '0';
               IF mode = single THEN
                   RSOX_zd := '1';
               END IF;
            ELSIF Count < TotalLOC THEN
               FFNeg_zd := '1';
               HFNeg_zd := '0';
               IF mode = single THEN
                   RSOX_zd := '0';
               END IF;
            ELSE
               FFNeg_zd := '0';
               HFNeg_zd := '0';
               IF mode = single THEN
                  RSOX_zd := '0';
               END IF;
            END IF;
            wr_inhibit := false;
            IF FFNeg_zd = '0' AND WNegIn = '0' THEN
                FF_pzd := '1';
            END IF;        
        END IF;
    END IF;

    IF falling_edge(FLNegIn) THEN
        IF RSIXIn = '1' THEN
            RDPoint := 0;
            Count := WRPoint;
            IF Count = 0 THEN
                EFNeg_zd := '0';
            ELSIF Count < Ael THEN
                FFNeg_zd := '1';
                RSOX_zd := '0';
                HFNeg_zd := '1';
            ELSIF Count < Half THEN
                FFNeg_zd := '1';
                RSOX_zd := '0';
                HFNeg_zd := '1';
            ELSIF Count < Aeh THEN
                FFNeg_zd := '1';
                RSOX_zd := '0';
                HFNeg_zd := '0';
            ELSIF Count < TotalLOC THEN
                FFNeg_zd := '1';
                RSOX_zd := '0';
                HFNeg_zd := '0';
            ELSE
                FFNeg_zd := '0';
                RSOX_zd := '1';
                HFNeg_zd := '0';
            END IF;
        END IF;
    ELSIF rising_edge(RSIXIn) AND mode = other_exp THEN
        IF wr_stat = inact THEN
            wr_stat := act;
        ELSE
            rd_stat := act;
        END IF;
    END IF;

    IF rising_edge(EF_pulse) THEN
         EFNeg_zd := '0';
         EF_pulse <= '0';
    ELSIF rising_edge(FF_pulse) THEN
         FFNeg_zd := '0';
         FF_pulse <= '0';
    END IF;

    IF falling_edge(SOCPIn) THEN
        DataDriveOut := 'Z';
    END IF;
    SO_zd <= DataDriveOut;

    ----------------------------------------------------------------------------
    -- Path Delay Section
    ----------------------------------------------------------------------------

    VitalPathDelay01 (
        OutSignal       => EF_pulse,
        OutSignalName   => "EF_pulse",
        OutTemp         => EF_pzd,
        GlitchData      => EFp_GlitchData,
        XOn             => false,
        MsgOn           => false,
        Paths           => (
        0 => (InputChangeTime   => WNeg'LAST_EVENT,
              PathDelay         => tpd_WNeg_EFNeg,
              PathCondition     => true)
        )
    );

    VitalPathDelay01 (
        OutSignal       => FF_pulse,
        OutSignalName   => "FF_pulse",
        OutTemp         => FF_pzd,
        GlitchData      => FFp_GlitchData,
        XOn             => false,
        MsgOn           => false,
        Paths           => (
        0 => (InputChangeTime   => SOCP'LAST_EVENT,
              PathDelay         => tpd_SOCP_FFNeg,
              PathCondition     => true)
        )
    );
  
    VitalPathDelay01 (
        OutSignal       => FFNegOut,
        OutSignalName   => "FFNeg",
        OutTemp         => FFNeg_zd,
        GlitchData      => FF_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
            0 => (InputChangeTime   => SOCP'LAST_EVENT,
                  PathDelay         => tpd_SOCP_FFNeg,
                  PathCondition     => TRUE),
            1 => (InputChangeTime   => WNeg'LAST_EVENT,
                  PathDelay         => tpd_WNeg_FFNeg,
                  PathCondition     => TRUE),
            2 => (InputChangeTime   => FF_pulse'LAST_EVENT,
                  PathDelay         => tpd_WNeg_EFNeg,
                  PathCondition     => true)
            )
    );

    VitalPathDelay01 (
        OutSignal       => EFNegOut,
        OutSignalName   => "EFNeg",
        OutTemp         => EFNeg_zd,
        GlitchData      => EF_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => SOCP'LAST_EVENT,
              PathDelay         => tpd_SOCP_EFNeg,
              PathCondition     => (mode = single)),
        1 => (InputChangeTime   => WNeg'LAST_EVENT,
              PathDelay         => tpd_WNeg_EFNeg,
              PathCondition     => (mode = single)),
        2 => (InputChangeTime   => SOCP'LAST_EVENT,
              PathDelay         => tpd_SOCP_EFNeg,
              PathCondition     => (mode /= single)),
        3 => (InputChangeTime   => WNeg'LAST_EVENT,
              PathDelay         => tpd_WNeg_EFNeg,
              PathCondition     => (mode /= single)),
        4 => (InputChangeTime   => EF_pulse'LAST_EVENT,
              PathDelay         => tpd_SOCP_EFNeg,
              PathCondition     => true)
        )
    );

    VitalPathDelay01 (
        OutSignal       => HFNegOut,
        OutSignalName   => "HFNeg",
        OutTemp         => HFNeg_zd,
        GlitchData      => HF_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => SOCP'LAST_EVENT,
              PathDelay         => tpd_SOCP_HFNeg,
              PathCondition     => (mode = single)),
        1 => (InputChangeTime   => WNeg'LAST_EVENT,
              PathDelay         => tpd_WNeg_HFNeg,
              PathCondition     => (mode = single)),
        2 => (InputChangeTime   => SOCP'LAST_EVENT,
              PathDelay         => tpd_SOCP_HFNeg,
              PathCondition     => (mode /= single)),
        3 => (InputChangeTime   => WNeg'LAST_EVENT,
              PathDelay         => tpd_WNeg_HFNeg,
              PathCondition     => (mode /= single))
        )
    );

    VitalPathDelay01 (
        OutSignal       => RSOXOut,
        OutSignalName   => "RSOX",
        OutTemp         => RSOX_zd,
        GlitchData      => RSOX_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => SOCP'LAST_EVENT,
              PathDelay         => tpd_SOCP_RSOX,
              PathCondition     => true),
        1 => (InputChangeTime   => WNeg'LAST_EVENT,
              PathDelay         => tpd_WNeg_RSOX,
              PathCondition     => true)
        )
    );

   VitalPathDelay01Z (
       OutSignal       => SOout,
       OutSignalName   => "SO",
       OutTemp         => SO_zd,
       Mode            => VitalTransport,
       GlitchData      => SO_GlitchData,
       Paths           => (
       0 => (InputChangeTime => SOCPIn'LAST_EVENT,
             PathDelay       => tpd_SOCP_SO,
             PathCondition   => TRUE)
       )
   );

       END PROCESS;
    END BLOCK;
END vhdl_behavioral;