idt72105.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
--  File Name: idt72105.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001, 2003 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     B. Bizic    01 Aug 08   Initial release
--    V1.1     B. Bizic    01 Sep 25   Corrected wr_inhibit
--    V1.2     R. Munden   03 Feb 15   Changed type of some _nwv signals to
--                                     satisfy ncvhdl 
--    V1.3     B.Bizic     03 May 28   Serial out bit order fixed,
--                                     FIFO almost full value corrected
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    FIFO
--  Technology: CMOS
--  Part:       IDT72105
-- 
--  Description: Parallel to Serial FIFO 256 x 16
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt72105 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D0               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D9               : VitalDelayType01 := VitalZeroDelay01;
        tipd_D10              : VitalDelayType01 := VitalZeroDelay01;
        tipd_D11              : VitalDelayType01 := VitalZeroDelay01;
        tipd_D12              : VitalDelayType01 := VitalZeroDelay01;
        tipd_D13              : VitalDelayType01 := VitalZeroDelay01;
        tipd_D14              : VitalDelayType01 := VitalZeroDelay01;
        tipd_D15              : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSNeg            : VitalDelayType01 := VitalZeroDelay01;
        tipd_WNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_SOCP             : VitalDelayType01 := VitalZeroDelay01;
        tipd_FLNeg            : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSIX             : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        -- tSOPD,tSOHZ,tSOLZ
        tpd_SOCP_SO           : VitalDelayType01Z := UnitDelay01Z;
        tpd_SOCP_FFNeg        : VitalDelayType01 := UnitDelay01;      -- tSOCFF
        tpd_SOCP_EFNeg        : VitalDelayType01 := UnitDelay01;      -- tSOCEF
        tpd_SOCP_HFNeg        : VitalDelayType01 := UnitDelay01;   -- tSOCF
        tpd_SOCP_RSOX         : VitalDelayType01 := UnitDelay01;      -- tSOXD
        tpd_WNeg_FFNeg        : VitalDelayType01 := UnitDelay01;      -- tWFF
        tpd_WNeg_EFNeg        : VitalDelayType01 := UnitDelay01;      -- tWEF
        tpd_WNeg_HFNeg        : VitalDelayType01 := UnitDelay01;   -- tWF
        tpd_WNeg_RSOX         : VitalDelayType01 := UnitDelay01;      -- tWF
        -- tsetup values: setup times
        tsetup_D0_WNeg        : VitalDelayType := UnitDelay;          -- tDS
        tsetup_RSIX_SOCP      : VitalDelayType := UnitDelay;          -- tSIXS
        tsetup_FLNeg_RSNeg    : VitalDelayType := UnitDelay;          -- tFLS
        tsetup_FLNeg_SOCP     : VitalDelayType := UnitDelay;          -- tDIRS 
        -- thold values: hold times
        thold_D0_WNeg         : VitalDelayType := UnitDelay;          -- tDH
        thold_FLNeg_RSNeg     : VitalDelayType := UnitDelay;          -- tFLH
        thold_FLNeg_SOCP      : VitalDelayType := UnitDelay;          -- tDIRH
        -- tpw values: pulse widths
        tpw_SOCP_negedge      : VitalDelayType := UnitDelay;          -- tSOCW
        tpw_SOCP_posedge      : VitalDelayType := UnitDelay;          -- tSOCW
        tpw_WNeg_negedge      : VitalDelayType := UnitDelay;          -- tWPW
        tpw_WNeg_posedge      : VitalDelayType := UnitDelay;          -- tWPW
        tpw_RSNeg_negedge     : VitalDelayType := UnitDelay;          -- tRS
        tpw_RSIX_posedge      : VitalDelayType := UnitDelay;          -- tSIXPW
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_WNeg_negedge  : VitalDelayType := UnitDelay;          -- tWC
        tperiod_SOCP_posedge  : VitalDelayType := UnitDelay;          -- tSOCP
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        RSNeg           : IN    std_ulogic := 'U';
        WNeg            : IN    std_ulogic := 'U';
        SOCP            : IN    std_ulogic := 'U';
        FLNeg           : IN    std_ulogic := 'U';
        RSIX            : IN    std_ulogic := 'U';
        D0              : IN    std_ulogic := 'U';
        D1              : IN    std_ulogic := 'U';
        D2              : IN    std_ulogic := 'U';
        D3              : IN    std_ulogic := 'U';
        D4              : IN    std_ulogic := 'U';
        D5              : IN    std_ulogic := 'U';
        D6              : IN    std_ulogic := 'U';
        D7              : IN    std_ulogic := 'U';
        D8              : IN    std_ulogic := 'U';
        D9              : IN    std_ulogic := 'U';
        D10             : IN    std_ulogic := 'U';
        D11             : IN    std_ulogic := 'U';
        D12             : IN    std_ulogic := 'U';
        D13             : IN    std_ulogic := 'U';
        D14             : IN    std_ulogic := 'U';
        D15             : IN    std_ulogic := 'U';
        SO              : OUT   std_ulogic := 'U';
        EFNeg           : OUT   std_ulogic := 'U';
        FFNeg           : OUT   std_ulogic := 'U';
        HFNeg           : OUT   std_ulogic := 'U';
        RSOX            : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt72105 : ENTITY IS TRUE;
END idt72105;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt72105 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "idt72105";
    CONSTANT MaxData        : NATURAL := 65536;
    CONSTANT TotalLOC       : NATURAL := 255;
    CONSTANT Half           : NATURAL := 128;
    CONSTANT Ael            : NATURAL := 32;
    CONSTANT Aeh            : NATURAL := 225;
    CONSTANT DataWidth      : NATURAL := 16;
    CONSTANT HiDbit         : NATURAL := 15;

    SIGNAL RSNeg_ipd        : std_ulogic := 'U';
    SIGNAL WNeg_ipd         : std_ulogic := 'U';
    SIGNAL SOCP_ipd         : std_ulogic := 'U';
    SIGNAL FLNeg_ipd        : std_ulogic := 'U';
    SIGNAL RSIX_ipd         : std_ulogic := 'U';
    SIGNAL D0_ipd           : std_ulogic := 'U';
    SIGNAL D1_ipd           : std_ulogic := 'U';
    SIGNAL D2_ipd           : std_ulogic := 'U';
    SIGNAL D3_ipd           : std_ulogic := 'U';
    SIGNAL D4_ipd           : std_ulogic := 'U';
    SIGNAL D5_ipd           : std_ulogic := 'U';
    SIGNAL D6_ipd           : std_ulogic := 'U';
    SIGNAL D7_ipd           : std_ulogic := 'U';
    SIGNAL D8_ipd           : std_ulogic := 'U';
    SIGNAL D9_ipd           : std_ulogic := 'U';
    SIGNAL D10_ipd          : std_ulogic := 'U';
    SIGNAL D11_ipd          : std_ulogic := 'U';
    SIGNAL D12_ipd          : std_ulogic := 'U';
    SIGNAL D13_ipd          : std_ulogic := 'U';
    SIGNAL D14_ipd          : std_ulogic := 'U';
    SIGNAL D15_ipd          : std_ulogic := 'U';

    SIGNAL RSNeg_nwv       : std_ulogic := 'U';
    SIGNAL WNeg_nwv        : std_ulogic := 'U';
    SIGNAL SOCP_nwv        : std_ulogic := 'U';
    SIGNAL FLNeg_nwv       : std_ulogic := 'U';
    SIGNAL RSIX_nwv        : std_ulogic := 'U';
    SIGNAL D0_nwv          : UX01 := 'U';
    SIGNAL D1_nwv          : UX01 := 'U';
    SIGNAL D2_nwv          : UX01 := 'U';
    SIGNAL D3_nwv          : UX01 := 'U';
    SIGNAL D4_nwv          : UX01 := 'U';
    SIGNAL D5_nwv          : UX01 := 'U';
    SIGNAL D6_nwv          : UX01 := 'U';
    SIGNAL D7_nwv          : UX01 := 'U';
    SIGNAL D8_nwv          : UX01 := 'U';
    SIGNAL D9_nwv          : UX01 := 'U';
    SIGNAL D10_nwv         : UX01 := 'U';
    SIGNAL D11_nwv         : UX01 := 'U';
    SIGNAL D12_nwv         : UX01 := 'U';
    SIGNAL D13_nwv         : UX01 := 'U';
    SIGNAL D14_nwv         : UX01 := 'U';
    SIGNAL D15_nwv         : UX01 := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_16 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_17 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_18 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_19 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_20 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_21 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_22 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_23 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_24 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_25 : VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_26 : VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_27 : VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_28 : VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_29 : VitalWireDelay (D13_ipd, D13, tipd_D13);
        w_30 : VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_31 : VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_37 : VitalWireDelay (SOCP_ipd, SOCP, tipd_SOCP);
        w_38 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
        w_39 : VitalWireDelay (RSIX_ipd, RSIX, tipd_RSIX);
        w_41 : VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg);
        w_42 : VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);

    END BLOCK;

        RSNeg_nwv      <= To_UX01 (s => RSNeg_ipd);
        WNeg_nwv       <= To_UX01 (s => WNeg_ipd);
        SOCP_nwv       <= To_UX01 (s => SOCP_ipd);
        FLNeg_nwv      <= To_UX01 (s => FLNeg_ipd);
        RSIX_nwv       <= To_UX01 (s => RSIX_ipd);
        D0_nwv         <= To_UX01 (s => D0_ipd);
        D1_nwv         <= To_UX01 (s => D1_ipd);
        D2_nwv         <= To_UX01 (s => D2_ipd);
        D3_nwv         <= To_UX01 (s => D3_ipd);
        D4_nwv         <= To_UX01 (s => D4_ipd);
        D5_nwv         <= To_UX01 (s => D5_ipd);
        D6_nwv         <= To_UX01 (s => D6_ipd);
        D7_nwv         <= To_UX01 (s => D7_ipd);
        D8_nwv         <= To_UX01 (s => D8_ipd);
        D9_nwv         <= To_UX01 (s => D9_ipd);
        D10_nwv        <= To_UX01 (s => D10_ipd);
        D11_nwv        <= To_UX01 (s => D11_ipd);
        D12_nwv        <= To_UX01 (s => D12_ipd);
        D13_nwv        <= To_UX01 (s => D13_ipd);
        D14_nwv        <= To_UX01 (s => D14_ipd);
        D15_nwv        <= To_UX01 (s => D15_ipd);

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
   Main: BLOCK

        PORT (
            RSNegIn     : IN    std_ulogic := 'U';
            WNegIn      : IN    std_ulogic := 'U';
            SOCPIn      : IN    std_ulogic := 'U';
            FLNegIn     : IN    std_ulogic := 'U';
            RSIXIn      : IN    std_ulogic := 'U';
            DataIn      : IN    std_logic_vector(HiDbit DOWNTO 0) :=
                                             (OTHERS => 'X');
            SOout       : OUT   std_ulogic := 'U';
            FFNegOut    : OUT   std_ulogic := 'U';
            EFNegOut    : OUT   std_ulogic := 'U';
            HFNegOut    : OUT   std_ulogic := 'U';
            RSOXOut     : OUT   std_ulogic := 'U'
              );
                                           
        PORT MAP (

            RSNegIn      => RSNeg_nwv,
            WNegIn       => WNeg_nwv,
            SOCPIn       => SOCP_nwv,
            FLNegIn      => FLNeg_nwv,
            RSIXIn       => RSIX_nwv,
            DataIn(0)    => D0_nwv,
            DataIn(1)    => D1_nwv,
            DataIn(2)    => D2_nwv,
            DataIn(3)    => D3_nwv,
            DataIn(4)    => D4_nwv,
            DataIn(5)    => D5_nwv,
            DataIn(6)    => D6_nwv,
            DataIn(7)    => D7_nwv,
            DataIn(8)    => D8_nwv,
            DataIn(9)    => D9_nwv,
            DataIn(10)   => D10_nwv,
            DataIn(11)   => D11_nwv,
            DataIn(12)   => D12_nwv,
            DataIn(13)   => D13_nwv,
            DataIn(14)   => D14_nwv,
            DataIn(15)   => D15_nwv,
            SOout        => SO, 
            FFNegOut     => FFNeg,
            EFNegOut     => EFNeg, 
            HFNegOut     => HFNeg, 
            RSOXOut      => RSOX