idt72845.vhd

VHDL的ram和fifo model code 包含众多的厂家

        END IF;
    END PROCESS;

    PAFNeg_zd <= not Almost_Fullint ;

    HlfFull_Resint <= '1' when
        ((WrP_GE_RdPint='1') and (WrP_mn_RdPint = HalfSize))
        or
        ((WrP_GE_RdPint='0') and (RdP_mn_WrPint = HalfSize))
        else '0';

    HlfFull_Setint <= '1' when
        ((WrP_GE_RdPint='1') and (WrP_mn_RdPint = HalfSize+1))
        or
        ((WrP_GE_RdPint='0') and (RdP_mn_WrPint = HalfSize-1))
        else '0';

    Half_Full_Flag: PROCESS (RSNeg, HlfFull_Resint, HlfFull_Setint)
    BEGIN
        IF (RSNeg='0') or (HlfFull_Resint='1')   THEN
            HFint <= '0';
        ELSIF (HlfFull_Setint='1') THEN
            HFint <= '1';
        END IF;
    END PROCESS;

    ----------------------------------------------------------------------------
    --  Expansion Logic                                                       --
    ----------------------------------------------------------------------------
    
    No_Expanint <= '1' when (WXINeg='0') and (RXINeg='0') else '0';

    Write_Enable_Mode:
          PROCESS(RSNeg,No_Expanint,FLNeg,Depth_Expanint,WXINeg,WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            IF (No_Expanint = '1') or (FLNeg='0')  THEN
                Write_Enableint <= '1' ;
            ELSE
                Write_Enableint <= '0' ;
            END IF;
        ELSIF (Depth_Expanint='1') and (WXINeg='0') THEN
                Write_Enableint <= '1' ;
        ELSIF WCLK'event and WCLK='1' THEN
            IF Depth_Expanint='1' THEN
                IF (Wr_RAM_Onint='1') and (Write_Pointerint=(RAMSize-1)) THEN
                    Write_Enableint <= '0';
                END IF;
            END IF;
        END IF;
    END PROCESS;

    Read_Enable_Mode: 
         PROCESS (RSNeg,No_Expanint,RXINeg, FLNeg, Depth_Expanint, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            IF (No_Expanint = '1') or (FLNeg='0')  THEN
                Read_Enableint <= '1' ;
            ELSE
                Read_Enableint <= '0' ;
            END IF;
        ELSIF (Depth_Expanint='1') and (RXINeg='0') THEN
                    Read_Enableint <= '1' ;
        ELSIF RCLK'event and RCLK='1' THEN
            IF Depth_Expanint='1' THEN
                IF (Rd_RAM_Onint='1') and (Read_Pointerint= (RAMSize-1)) THEN
                    Read_Enableint <= '0';
                END IF;
            END IF;
        END IF;
    END PROCESS;

    Read_Enable_Delay:PROCESS (RSNeg, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Read_En_Delint <= '0' ;
        ELSIF RCLK'event and RCLK='1' THEN
            Read_En_Delint <= Read_Enableint ;
        END IF;
    END PROCESS;

    Depth_Expansion_Mode: PROCESS (RSNeg, No_Expanint)
    BEGIN
        IF RSNeg = '0' THEN
            IF (No_Expanint = '1') THEN
                Depth_Expanint <='0';
            ELSE
                Depth_Expanint <='1';
            END IF;
        END IF;
    END PROCESS;

    -- WXONeg Output
    ----------------------------------------------------------------------------

    WXOHFNeg_zd <= not WXOint when (Depth_Expanint='1') else
                   not HFint ;

    WX0_Trigger1 : PROCESS (RSNeg,WXO_Tg2int,WCLK)
    BEGIN
        IF (RSNeg='0') or (WXO_Tg2int='1') THEN
            WXO_Tg1int <= '0';
        ELSIF WCLK'event and WCLK='1' THEN
                IF (Wr_RAM_Onint='1') and (Write_Pointerint=(RAMSize-1)) THEN
                    WXO_Tg1int<= '1';
                END IF;
        END IF;
    END PROCESS;

    WX0_Trigger2: PROCESS (RSNeg, WCLK)
    BEGIN
        IF (RSNeg='0') THEN
            WXO_Tg2int <= '0';
        ELSIF WCLK'event and WCLK='0' THEN
            WXO_Tg2int <= WXO_Tg1int;
        END IF;
    END PROCESS;

    WXOint<= WXO_Tg1int and (not WXO_Tg2int);

    -- RXONeg_zd Output
    ----------------------------------------------------------------------------
    RX0_Trigger1 : PROCESS (RSNeg,RXO_Tg2int,RCLK)
    BEGIN
        IF (RSNeg='0') or (RXO_Tg2int='1') THEN
            RXO_Tg1int <= '0';
        ELSIF RCLK'event and RCLK='1' THEN
                IF (Rd_RAM_Onint='1') and (Read_Pointerint=(RAMSize-1)) THEN
                    RXO_Tg1int<= '1';
                END IF;
        END IF;
    END PROCESS;

    RX0_Trigger2: PROCESS (RSNeg, RCLK)
    BEGIN
        IF (RSNeg='0') THEN
            RXO_Tg2int <= '0';
        ELSIF RCLK'event and RCLK='0' THEN
            RXO_Tg2int <= RXO_Tg1int;
        END IF;
    END PROCESS;

    RXONeg_zd <= not (RXO_Tg1int and (not RXO_Tg2int)) ;

    ----------------------------------------------------------------------------
    --  Output Logic                                                          --
    ----------------------------------------------------------------------------

    Zerosint <=(others =>'0');
    
    Data_Outint <= RAM(Read_Pointerint) 
                   when (LDNeg='1') and (Emptyint='0') else
        Zerosint&PAE_Offset_Regint
                   when (LDNeg='0') and (Rd_Offset_Pntint='0') else
        Zerosint&PAF_Offset_Regint
                   when (LDNeg='0') and (Rd_Offset_Pntint='1') else
        Output_Regint;

    Output_Register: PROCESS (RSNeg, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Output_Regint <= (others =>'0') ;
        ELSIF RCLK'event and RCLK='1' THEN
                IF (RENNeg='0') and (Read_Enableint='1') THEN
                    Output_Regint <= Data_Outint;
                END IF;
        END IF;
    END PROCESS;

    Q_zd <= Output_Regint when (OENeg='0') and (Read_En_Delint='1') else 
            (others => 'Z') ;

    ----------------------------------------------------------------------------
    -- Additional Delayed Signals                                             --
    ----------------------------------------------------------------------------
    Write_PRint_DEL <= Write_PRint after tdevice_SKEW2; 
    Read_PRint_DEL  <= Read_PRint  after tdevice_SKEW1;
    Read_Flint_DEL  <= Read_Flint  after tdevice_SKEW1;
    Write_Flint_DEL <= Write_Flint after tdevice_SKEW2;
    
    ----------------------------------------------------------------------------
    -- Path Delay Section                                                     --
    ----------------------------------------------------------------------------

    -- Path delay for EFNeg ;
    PathDelay_EFNeg: PROCESS (EFNeg_zd)
        VARIABLE EFNeg_GlitchData: VitalGlitchDataType;
    BEGIN
        VitalPathDelay01(
            OutSignal    => EFNeg,
            OutSignalName=> "EFNeg",
            OutTemp      => EFNeg_zd,
            GlitchData   => EFNeg_GlitchData,
            Paths        =>
                ( 
                  0 => (InputChangeTime => RSNeg'LAST_EVENT,--
                        PathDelay       => tpd_RSNeg_EFNeg,--tRSF
                        PathCondition   => TRUE
                       ),
                  1 => (InputChangeTime => RCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_EFNeg,--tREF
                        PathCondition   => TRUE
                       )
                )
        );
    END PROCESS;

    -- Path delay for PAENeg ;
    PathDelay_PAENeg: PROCESS (PAENeg_zd)
        VARIABLE PAENeg_GlitchData: VitalGlitchDataType;
    BEGIN
        VitalPathDelay01(
            OutSignal    => PAENeg,
            OutSignalName=> "PAENeg",
            OutTemp      => PAENeg_zd,
            GlitchData   => PAENeg_GlitchData,
            Paths        =>
                ( 
                  0 => (InputChangeTime => RSNeg'LAST_EVENT,--
                        PathDelay       => tpd_RSNeg_EFNeg,--tRSF
                        PathCondition   => TRUE
                       ),
                  1 => (InputChangeTime => RCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_PAENeg,--tPAE
                        PathCondition   => RENNeg='0'
                       ),
                  2 => (InputChangeTime => WCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_PAENeg,--tPAE
                        PathCondition   => WENNeg='0'
                       )
                )
        );
    END PROCESS;

    -- Path delay for PAFNeg ;
    PathDelay_PAFNeg: PROCESS (PAFNeg_zd)
        VARIABLE PAFNeg_GlitchData: VitalGlitchDataType;
    BEGIN
        VitalPathDelay01(
            OutSignal    => PAFNeg,
            OutSignalName=> "PAFNeg",
            OutTemp      => PAFNeg_zd,
            GlitchData   => PAFNeg_GlitchData,
            Paths        =>
                (
                  0 => (InputChangeTime => RSNeg'LAST_EVENT,--
                        PathDelay       => tpd_RSNeg_EFNeg,--tRSF
                        PathCondition   => TRUE
                       ),
                  1 => (InputChangeTime => RCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_PAFNeg,--tPAF
                        PathCondition   => RENNeg='0'
                       ),
                  2 => (InputChangeTime => WCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_PAFNeg,--tPAF
                        PathCondition   => WENNeg='0'
                       )
                )
        );
    END PROCESS;

    -- Path delay for FFNeg  ;
    PathDelay_FFNeg: PROCESS (FFNeg_zd)
        VARIABLE FFNeg_GlitchData: VitalGlitchDataType;
    BEGIN
        VitalPathDelay01(
            OutSignal    => FFNeg,
            OutSignalName=> "FFNeg",
            OutTemp      => FFNeg_zd,
            GlitchData   => FFNeg_GlitchData,
            Paths        =>
                (
                  0 => (InputChangeTime => RSNeg'LAST_EVENT,--
                        PathDelay       => tpd_RSNeg_EFNeg,--tRSF
                        PathCondition   => TRUE
                       ),
                  1 => (InputChangeTime => WCLK'LAST_EVENT,--
                        PathDelay       => tpd_WCLK_FFNeg,--tWFF
                        PathCondition   => TRUE
                       )
                )
        );
    END PROCESS;

    -- Path delay for WXOHFNeg ;
    PathDelay_WXOHFNeg: PROCESS (WXOHFNeg_zd)
        VARIABLE WXOHFNeg_GlitchData: VitalGlitchDataType;
    BEGIN
        VitalPathDelay01(
            OutSignal    => WXOHFNeg,
            OutSignalName=> "WXOHFNeg",
            OutTemp      => WXOHFNeg_zd,
    	    Mode 	 => VitalTransport,
            GlitchData   => WXOHFNeg_GlitchData,
            Paths        =>   -- HF
                (
                  0 => (InputChangeTime => RSNeg'LAST_EVENT,--
                        PathDelay       => tpd_RSNeg_EFNeg,--tRSF
                        PathCondition   => TRUE
                       ),
                  1 => (InputChangeTime => RCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_WXOHFNeg,--tHF
                        PathCondition   => (Depth_Expanint ='0')
                                            and (RENNeg='0')
                       ),
                  2 => (InputChangeTime => WCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_WXOHFNeg,--tHF
                        PathCondition   => (Depth_Expanint ='0')
                                           and (WENNeg='0')
                       ),                                -- WXO
                  3 => (InputChangeTime => WCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_RXONeg,--tXO
                        PathCondition   => (Depth_Expanint ='1')
                       )
                )
        );
    END PROCESS;

    -- Path delay for RXONeg ;
    PathDelay_RXONeg: PROCESS (RXONeg_zd)
        VARIABLE RXONeg_GlitchData: VitalGlitchDataType;
    BEGIN
        VitalPathDelay01(
            OutSignal    => RXONeg,
            OutSignalName=> "RXONeg",
            OutTemp      => RXONeg_zd,
    	    Mode 	 => VitalTransport,
            GlitchData   => RXONeg_GlitchData,
            Paths        =>
                ( 
                  0 => (InputChangeTime => RSNeg'LAST_EVENT,--
                        PathDelay       => tpd_RSNeg_EFNeg,--tRSF
                        PathCondition   => TRUE
                       ),
                  1 => (InputChangeTime => RCLK'LAST_EVENT,--
                        PathDelay       => tpd_RCLK_RXONeg,--tXO
                        PathCondition   => TRUE
                       )
                )
        );
    END PROCESS;

    -- Path delay for Q      ;

    PathDelay_Q_Gen: FOR i IN RAMWordLength-1 DOWNTO 0 GENERATE

        PathDelay_Q: PROCESS (Q_zd(i))
            VARIABLE Q_GlitchData: VitalGlitchDataType;
        BEGIN
            VitalPathDelay01Z(
                OutSignal    => Q(i),
                OutSignalName=> "Q",
                OutTemp      => Q_zd(i),
                GlitchData   => Q_GlitchData,
                Paths        =>
                    (
                      0 => (InputChangeTime => OENeg'LAST_EVENT,--
                            PathDelay       => tpd_OENeg_Q0,-- tOLZ/tOE/tOHZ
                            PathCondition  => TRUE
                           ),
                      1 => (InputChangeTime => RSNeg'LAST_EVENT,--
                            PathDelay       => tpd_RSNeg_Q0,--tRSF
                            PathCondition  => TRUE
                           ),
                      2 => (InputChangeTime => RCLK'LAST_EVENT,--
                            PathDelay       => tpd_RCLK_Q0,--tA
                            PathCondition  => (RENNeg='0')
                           )
                    ),
                MsgOn   => False
            );
        END PROCESS;
    END GENERATE;

END BLOCK VITALBehavior;

END vhdl_behavioral;