idt72845.vhd

VHDL的ram和fifo model code 包含众多的厂家

        WENNeg  : IN    std_logic := 'X' ;
        RCLK    : IN    std_logic := 'X' ;
        RENNeg  : IN    std_logic := 'X' ;
        OENeg   : IN    std_logic := 'X' ;
        LDNeg   : IN    std_logic := 'X' ;
        WXINeg  : IN    std_logic := 'X' ;
        RXINeg  : IN    std_logic := 'X' ;

        EFNeg   : OUT   std_logic := 'U' ;
        PAENeg  : OUT   std_logic := 'U' ;
        PAFNeg  : OUT   std_logic := 'U' ;
        FFNeg   : OUT   std_logic := 'U' ;
        WXOHFNeg: OUT   std_logic := 'U' ;
        RXONeg  : OUT   std_logic := 'U' ;
        Q       : OUT   RAM_Word := (OTHERS => 'U')
    );

    PORT MAP (
        D(0)     => D0_ipd,
        D(1)     => D1_ipd,
        D(2)     => D2_ipd,
        D(3)     => D3_ipd,
        D(4)     => D4_ipd,
        D(5)     => D5_ipd,
        D(6)     => D6_ipd,
        D(7)     => D7_ipd,
        D(8)     => D8_ipd,
        D(9)     => D9_ipd,
        D(10)    => D10_ipd,
        D(11)    => D11_ipd,
        D(12)    => D12_ipd,
        D(13)    => D13_ipd,
        D(14)    => D14_ipd,
        D(15)    => D15_ipd,
        D(16)    => D16_ipd,
        D(17)    => D17_ipd,
        RSNeg    => RSNeg_ipd,
        WCLK     => WCLK_ipd,
        WENNeg   => WENNeg_ipd,
        RCLK     => RCLK_ipd,
        RENNeg   => RENNeg_ipd,
        OENeg    => OENeg_ipd,
        LDNeg    => LDNeg_ipd,
        WXINeg   => WXINeg_ipd,
        RXINeg   => RXINeg_ipd,

        EFNeg    => EFNeg,
        PAENeg   => PAENeg,
        PAFNeg   => PAFNeg,
        FFNeg    => FFNeg,
        WXOHFNeg => WXOHFNeg,
        RXONeg   => RXONeg,
        Q(0)     => Q0,
        Q(1)     => Q1,
        Q(2)     => Q2,
        Q(3)     => Q3,
        Q(4)     => Q4,
        Q(5)     => Q5,
        Q(6)     => Q6,
        Q(7)     => Q7,
        Q(8)     => Q8,
        Q(9)     => Q9,
        Q(10)    => Q10,
        Q(11)    => Q11,
        Q(12)    => Q12,
        Q(13)    => Q13,
        Q(14)    => Q14,
        Q(15)    => Q15,
        Q(16)    => Q16,
        Q(17)    => Q17
    );
        -- zero delayed outputs;
        -- actual outports are assigned in Path Delay Section

    SIGNAL  EFNeg_zd   : std_logic ;
    SIGNAL  PAENeg_zd  : std_logic ;
    SIGNAL  PAFNeg_zd  : std_logic ;
    SIGNAL  FFNeg_zd   : std_logic ;
    SIGNAL  WXOHFNeg_zd: std_logic ;
    SIGNAL  RXONeg_zd  : std_logic ;
    SIGNAL  Q_zd       : RAM_Word  ;
    

BEGIN -- VitalBehavior block


    ----------------------------------------------------------------------------
    -- Timing Check Section                                                   --
    ----------------------------------------------------------------------------

    TimingChecks: PROCESS (D, RSNeg, WCLK, WENNeg, RCLK, RENNeg,
                           OENeg, LDNeg, WXINeg, RXINeg)

        -- Timing Check Variables

        -- Pulse Width & Period Check Variables

        VARIABLE Pviol_WCLK          : X01 := '0';
        VARIABLE PD_WCLK             : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_RCLK          : X01 := '0';
        VARIABLE PD_RCLK             : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_RSNeg         : X01 := '0';
        VARIABLE PD_RSNeg            : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_WXINeg        : X01 := '0';
        VARIABLE PD_WXINeg           : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_RXINeg        : X01 := '0';
        VARIABLE PD_RXINeg           : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

       -- Setup/Hold Check Variables

        VARIABLE Tviol_D0_WCLK       : X01 := '0';
        VARIABLE TD_D0_WCLK          : VitalTimingDataType;

        VARIABLE Tviol_WENNeg_WCLK   : X01 := '0';
        VARIABLE TD_WENNeg_WCLK      : VitalTimingDataType;

        VARIABLE Tviol_RENNeg_RCLK   : X01 := '0';
        VARIABLE TD_RENNeg_RCLK      : VitalTimingDataType;

        VARIABLE Tviol_LDNeg_WCLK    : X01 := '0';
        VARIABLE TD_LDNeg_WCLK       : VitalTimingDataType;

        VARIABLE Tviol_LDNeg_RCLK    : X01 := '0';
        VARIABLE TD_LDNeg_RCLK       : VitalTimingDataType;

        VARIABLE Tviol_WENNeg_RSNeg  : X01 := '0';
        VARIABLE TD_WENNeg_RSNeg     : VitalTimingDataType;

        VARIABLE Tviol_RENNeg_RSNeg  : X01 := '0';
        VARIABLE TD_RENNeg_RSNeg     : VitalTimingDataType;

        VARIABLE Tviol_LDNeg_RSNeg   : X01 := '0';
        VARIABLE TD_LDNeg_RSNeg      : VitalTimingDataType;

        VARIABLE Tviol_WXINeg_WCLK   : X01 := '0';
        VARIABLE TD_WXINeg_WCLK      : VitalTimingDataType;

        VARIABLE Tviol_RXINeg_RCLK   : X01 := '0';
        VARIABLE TD_RXINeg_RCLK      : VitalTimingDataType;


        -- Recovery Check Variables

        VARIABLE Rviol_WENNeg_RSNeg : X01 := '0';
        VARIABLE RD_WENNeg_RSNeg    : VitalTimingDataType;

        VARIABLE Rviol_RENNeg_RSNeg : X01 := '0';
        VARIABLE RD_RENNeg_RSNeg    : VitalTimingDataType;

        VARIABLE Rviol_LDNeg_RSNeg  : X01 := '0';
        VARIABLE RD_LDNeg_RSNeg     : VitalTimingDataType;
        
        -- Skew Check Variables

        VARIABLE Sviol_Skew1        : X01 := '0';
        VARIABLE Sviol_Skew2        : X01 := '0';
        
        VARIABLE WCLK_Last_Front    : time :=0 ns;
        VARIABLE RCLK_Last_Front    : time :=0 ns;

        -- Violation variable (used to OR all individual violations)

        VARIABLE Violation           : X01 := '0';

    BEGIN  -- timing checks process

        IF  (TimingChecksOn) THEN

              Pviol_WCLK          := '0';
              Pviol_RCLK          := '0';
              Pviol_RSNeg         := '0';
              Pviol_WXINeg        := '0';
              Pviol_RXINeg        := '0';

              Tviol_D0_WCLK       := '0';
              Tviol_WENNeg_WCLK   := '0';
              Tviol_RENNeg_RCLK   := '0';
              Tviol_LDNeg_WCLK    := '0';
              Tviol_LDNeg_RCLK    := '0';
              Tviol_WENNeg_RSNeg  := '0';
              Tviol_RENNeg_RSNeg  := '0';
              Tviol_LDNeg_RSNeg   := '0';
              Tviol_WXINeg_WCLK   := '0';
              Tviol_RXINeg_RCLK   := '0';

              Rviol_WENNeg_RSNeg  := '0';
              Rviol_RENNeg_RSNeg  := '0';
              Rviol_LDNeg_RSNeg   := '0';
              
              Sviol_Skew1         := '0';
              Sviol_Skew2         := '0';

            --1 WCLK pulse (low & high) width and period check
            --  (tCLK, tCLKH, tCLKL)

            IF WCLK'event THEN 

            VitalPeriodPulseCheck (
                TestSignal      => WCLK,
                TestSignalName  => "WCLK",
                Period          => tperiod_RCLK_posedge,
                PulseWidthHigh  => tpw_RCLK_posedge,
                PulseWidthLow   => tpw_RCLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_WCLK);
             END IF;

            --2 RCLK pulse (low & high) width and period check
            --  (tCLK, tCLKH, tCLKL)
            IF RCLK'event THEN

            VitalPeriodPulseCheck (
                TestSignal      => RCLK,
                TestSignalName  => "RCLK",
                Period          => tperiod_RCLK_posedge,
                PulseWidthHigh  => tpw_RCLK_posedge,
                PulseWidthLow   => tpw_RCLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RCLK);
            END IF;

            --3 RSNeg low pulse width check (tRS)

            IF RSNeg'event THEN
            VitalPeriodPulseCheck (
                TestSignal      => RSNeg,
                TestSignalName  => "RSNEg",
                PulseWidthLow   => tpw_RSNeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RSNeg);
            END IF;

            --4 WXINeg low pulse width check (tXI)

            IF WXINeg'event THEN
            VitalPeriodPulseCheck (
                TestSignal      => WXINeg,
                TestSignalName  => "WXINEg",
                PulseWidthLow   => tpw_RXINeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_WXINeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_WXINeg);
            END IF;

            --5 RXIeg low pulse width check (tXI)

            IF RXINeg'event THEN
            VitalPeriodPulseCheck (
                TestSignal      => RXINeg,
                TestSignalName  => "RXINEg",
                PulseWidthLow   => tpw_RXINeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RXINeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RXINeg);
            END IF;

            --6 D/WCLK setup/hold time check (tDS, tDH)
            IF D'event OR (WCLK'event AND WCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => D,
                TestSignalName  => "D",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupHigh       => tsetup_D0_WCLK_noedge_posedge,
                SetupLow        => tsetup_D0_WCLK_noedge_posedge,
                HoldHigh        => thold_D0_WCLK_noedge_posedge,
                HoldLow         => thold_D0_WCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_D0_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_D0_WCLK);
            END IF;

            --7 WENNeg/WCLK setup/hold time check (tENS, tENH)
            IF WENNeg'event OR (WCLK'event AND WCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => WENNEg,
                TestSignalName  => "WENNeg",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupLow        => tsetup_RENNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_RENNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WENNeg_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WENNeg_WCLK);
            END IF;

            --8 RENNeg/RCLK setup/hold time check (tENS, tENH)
            IF RENNeg'event OR (RCLK'event AND RCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => RENNEg,
                TestSignalName  => "RENNeg",
                RefSignal       => RCLK,
                RefSignalName   => "RCLK",
                SetupLow        => tsetup_RENNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_RENNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_RENNeg_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RENNeg_RCLK);
            END IF;

            --9 LDNeg/WCLK setup/hold time check (tLDS, tLDH)
            IF LDNeg'event OR (WCLK'event AND WCLK = '1' AND WENNeg ='0') THEN

            VitalSetupHoldCheck (
                TestSignal      => LDNEg,
                TestSignalName  => "LDNeg",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupLow        => tsetup_LDNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_LDNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LDNeg_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LDNeg_WCLK);
            END IF;

            --10 LDNeg/RCLK setup/hold time check (tLDS, tLDH)
            IF LDNeg'event OR (RCLK'event AND RCLK = '1' AND RENNeg ='0') THEN

            VitalSetupHoldCheck (
                TestSignal      => LDNEg,
                TestSignalName  => "LDNeg",
                RefSignal       => RCLK,
                RefSignalName   => "RCLK",
                SetupLow        => tsetup_LDNeg_RCLK_noedge_posedge,
                HoldHigh        => thold_LDNeg_RCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LDNeg_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LDNeg_RCLK);
            END IF;

            --11 RENNeg/RSNeg setup time check (tRSS)