idt72271.vhd

VHDL的ram和fifo model code 包含众多的厂家

                     std_logic_vector(to_slv(1, MSBS+1));

    ELSE
        AlmostEmptyCondInt <= cond1;
        AlmostFullCondInt <= FIFOSize - cond1;
        ParProgInt <= '1';
        LSBPAEInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond1, LSBS+1));
        LSBPAFInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond1, LSBS+1));
        MSBPAEInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(0, MSBS+1));
        MSBPAFInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(0, MSBS+1));
    END IF;
ELSE

    IF PaeenDop = '1' THEN
        PAEEnable <= '1';
        VirtualWRAEF <= '0';
    END IF;

    IF WCLK'event AND WCLK = '1' THEN

        IF VirtualWRAFF = '1' THEN
            PafenDop <= '1';
            VirtualWRAFF <= '0';
        END IF;

        IF PafenDop = '1' THEN
            PAFEnable <= '1';
            PafenDop <= '0';
        END IF;

        IF ParProgInt = '1' THEN
           IF LDNeg ='0' AND WENNeg = '0' THEN
               CASE FrontNumInt is
               WHEN "00000" =>
                   PAEEnable <= '0';
                   FrontNumInt <= "00001";
                   LSBPAEInt(LSBS DOWNTO 0) <= DataInInt(LSBS DOWNTO 0);
                   AlmostEmptyCondInt <= to_nat((
                       MSBPAEInt(MSBS DOWNTO 0) & DataInInt(LSBS DOWNTO 0)));
               WHEN "00001" =>
                   FrontNumInt <= "00010";
                   MSBPAEInt(MSBS DOWNTO 0) <= DataInInt(MSBS DOWNTO 0);
                   AlmostEmptyCondInt <= to_nat((
                      DataInInt(MSBS DOWNTO 0) & LSBPAEInt(LSBS DOWNTO 0)));
                   VirtualWRAEF <= '1' AFTER tdevice_SKEW2;
               WHEN "00010" =>
                   PAFEnable <= '0';
                   FrontNumInt <= "00011";
                   LSBPAFInt(LSBS DOWNTO 0) <= DataInInt(LSBS DOWNTO 0);
                   AlmostFullCondInt <= FIFOSize - to_nat((
                      MSBPAFInt(MSBS DOWNTO 0) & DataInInt(LSBS DOWNTO 0)));
               WHEN "00011" =>
                   FrontNumInt <= "00000";
                   MSBPAFInt(MSBS DOWNTO 0) <= DataInInt(MSBS DOWNTO 0);
                   ProgFinishedInt <= '1';
                   AlmostFullCondInt <= FIFOSize - to_nat((
                      DataInInt(MSBS DOWNTO 0) & LSBPAFInt(LSBS DOWNTO 0)));
                   VirtualWRAFF <= '1';
               WHEN others =>
                   NULL;
               END CASE;
           END IF;
       ELSE
           LSBPAEInt <= LSBPAE1Int;
           MSBPAEInt <= MSBPAE1Int;
           LSBPAFInt <= LSBPAF1Int;
           MSBPAFInt <= MSBPAF1Int;
           IF LDNeg ='0' AND SENNeg = '0' AND ProgFinishedInt = '0' THEN
               PAEEnable <= '0';
               PAFEnable <= '0';
               FrontNumInt <= std_logic_vector(to_slv(
                            to_nat((FrontNumInt)) + 1, 5));
               IF to_nat((FrontNumInt)) < SerialRegInt'high THEN
                   SerialRegInt(to_nat((FrontNumInt))) <= SerialInputInt;
               ELSE
                   SerialRegInt(to_nat((FrontNumInt))) <= SerialInputInt;
                   AlmostEmptyCondInt <= to_nat((
                      MSBPAEInt(MSBS DOWNTO 0) & LSBPAEInt(LSBS DOWNTO 0)));
                   AlmostFullCondInt <= FIFOSize - to_nat((
                      SerialInputInt & MSBPAF1Int(MSBS - 1 DOWNTO 0) &
                      LSBPAFInt(LSBS DOWNTO 0)));
                   ProgFinishedInt <= '1';
                   FrontNumInt <= "00000";
                   VirtualWRAEF <= '1' AFTER tdevice_SKEW2;
                   VirtualWRAFF <= '1';
               END IF;
           END IF;
       END IF;
    END IF;
END IF;
END PROCESS;

Output_latch:PROCESS(MRSNeg, OENeg, OutputRegisterInt, OutputValidInt)
BEGIN
IF OENeg = '0' THEN
    OutputValidInt <= '1';
ELSE
    OutputValidInt <= '0';
END IF;

IF MRSNeg = '0' THEN
    IF OENeg = '1' THEN
        DataOutInt <= "ZZZZZZZZZ";
    ELSE
        DataOutInt<= "000000000";
    END IF;
ELSE
    IF OutputValidInt = '1' THEN
        DataOutInt <= OutputRegisterInt;
    ELSE
        DataOutInt <= "ZZZZZZZZZ";
    END IF;
END IF;
END PROCESS;

First_word: PROCESS(WCLK, MRSNeg, ReadFirstAfterRTInt)
BEGIN

IF MRSNeg = '0' OR ReadFirstAfterRTInt = '1' THEN
    FWFTFirstWordInt <= '0';
ELSIF RTEndInt = '1' and ModeInt = '1' THEN
    FWFTFirstWordInt <= '1';
ELSIF WCLK'event AND WCLK = '1' THEN
    IF ModeInt = '1' AND OutputReadyInt = '1' and
                FWFTFirstWordInt = '0' AND WENNeg = '0' THEN
        FWFTFirstWordInt <= '1';
        InpRegInt <= DataInInt;
    END IF;
END IF;
END PROCESS;

First_word_WR: PROCESS(MRSNeg, FWFTFirstWordInt, RCLK)
BEGIN
IF MRSNeg = '0' THEN
    FirstWordWritedInt <= '0';
ELSIF FWFTFirstWordInt = '1' THEN
    FirstWordWritedInt <= '1';
ELSIF RCLK'event AND RCLK = '1' THEN
    IF RTNeg = '0' OR (EmptyFlagInt = '0' AND DiffInt = 0) THEN
        FirstWordWritedInt <= '0';
    END IF;
END IF;
END PROCESS;

Read_Write: PROCESS(WCLK, HalfFull1Int, MRSNeg, PRSNeg, RCLK, FullFlagInt)

variable FIFO0Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO1Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO2Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO3Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO4Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO5Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO6Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO7Int          :  std_logic_vector(FIFOSize DOWNTO 0);
variable FIFO8Int          :  std_logic_vector(FIFOSize DOWNTO 0);

BEGIN

-- SUBPROCESS Write

IF MRSNeg = '0' THEN
    WRPointerInt <= 0;
    IF FWFTSI = '1' THEN
        ModeInt <= '1'; -- FWFT;
        FullFlagInt <= '1';
        HFInt <= '1';
        PAFInt <= '1';
        PAF1Int <= '1';
        WRIntoEmptyInt <= '0';
        FullFlag1Int <= '0';
    ELSE
        ModeInt <= '0'; -- IDT;
        FullFlagInt <= '1';
        HFInt <= '1';
        PAFInt <= '1';
        PAF1Int <= '1';
        WRIntoEmptyInt <= '0';
        FullFlag1Int <= '1';
    END IF;
ELSIF PRSNeg = '0' THEN
    WRPointerInt <= 0;
    IF ModeInt ='1' THEN
        FullFlagInt <= '1';
        FullFlag1Int <= '0';
        HFInt <= '1';
        PAFInt <= '1';
        PAF1Int <= '1';
    ELSE
        FullFlagInt <= '1';
        FullFlag1Int <= '0';
        HFInt <= '1';
        PAFInt <= '1';
        PAF1Int <= '1';
    END IF;
ELSE
    IF (AfterRTInt = '1' AND DiffInt >= HalfFullCondInt) AND
        ((ModeInt = '0' AND RENNeg = '0' AND RCLK = '1') OR
        (ModeInt = '1')) THEN
        HFInt <= '0';
    ELSIF HalfFull1Int = '0' THEN
        HFInt <= '1';
    END IF;

    IF WCLK'event AND WCLK = '1'  THEN

        IF ReadFromFullInt = '0' THEN
            FullFlag1Int <= '1';
        END IF;

        IF FullFlag1Int = '1' THEN
            FullFlagInt <= '1';
        END IF;

        IF EmptyFlagInt ='1' THEN
            WRIntoEmptyInt <= '0';
        END IF;

        IF PAEInt ='0' THEN
            AEFInt <= '0';
        END IF;

        IF PAF2Int = '0' THEN
            PAF2Int <= '1';
        END IF;


        IF AfterRTSkew2Int = '1' THEN
            IF PAF2Int = '0' OR RTAFFInt = '0' THEN
               PAF1Int <= '0';
            END IF;
            IF AFFInt = '1' THEN
                PAF1Int <= '1';
            END IF;
        END IF;

        IF PAF1Int = '0' THEN
            PAFInt <= '0';
        ELSE
            PAFInt <= '1';
        END IF;

        IF WENNeg = '0' AND WrEnInt ='1' AND LDNeg = '1' THEN

            IF (EmptyFlagInt = '0' AND  ModeInt = '0') or
                  (OutputReadyInt = '1' AND  ModeInt = '1') THEN
               WRIntoEmptyInt <= '1';
            END IF;

            IF FirstWordWritedInt = '1' OR ModeInt = '0' THEN

                IF DiffInt >=  AlmostFullCondInt - 1  THEN
                    PAF2Int <= '0';
                END IF;

                IF WRPointerInt = FIFOSize - 1 THEN
                   WRPointerInt <= 0;
                ELSE
                   WRPointerInt <= WRPointerInt + 1;
                END IF;

                IF DiffInt >= AlmostEmptyCondInt THEN
                   AEFInt <= '1' AFTER tdevice_SKEW2;
                END IF;

                IF DiffInt = FIFOSize - 1 THEN
                   FullFlagInt <= '0';
                   FullFlag1Int <= '0';
                END IF;

                IF DiffInt >= HalfFullCondInt THEN
                    HFInt <= '0';
                END IF;

                FIFO0Int(WRPointerInt) := DataInInt(0);
                FIFO1Int(WRPointerInt) := DataInInt(1);
                FIFO2Int(WRPointerInt) := DataInInt(2);
                FIFO3Int(WRPointerInt) := DataInInt(3);
                FIFO4Int(WRPointerInt) := DataInInt(4);
                FIFO5Int(WRPointerInt) := DataInInt(5);
                FIFO6Int(WRPointerInt) := DataInInt(6);
                FIFO7Int(WRPointerInt) := DataInInt(7);
                FIFO8Int(WRPointerInt) := DataInInt(8);
            END IF;
        END IF;
    END IF;
END IF;

-- END SUBPROCESS Write


-- SUBPROCESS Read

IF MRSNeg = '0' THEN
    RTBeginInt <= '0';
    OutputRegisterInt <= "000000000";
    RDPointerInt <= 0;
    ReadFirstAfterRTInt <= '0';
    IF FWFTSI = '1' THEN
        EmptyFlagInt <= '0';
        PAEInt <= '0';
        PAE1Int <= '0';
    ELSE
        EmptyFlagInt <= '0';
        PAEInt <= '0';
        PAE1Int <= '0';
    END IF;
ELSIF PRSNeg = '0' THEN
    OutputRegisterInt <= "000000000";
    RDPointerInt <= 0;
    IF ModeInt = '1' THEN
        EmptyFlagInt <= '0';
        PAEInt <= '0';
        PAE1Int <= '0';
    ELSE
        EmptyFlagInt <= '0';
        PAEInt <= '0';
        PAE1Int <= '0';
    END IF;
ELSE
    IF FullFlagInt = '1' THEN
        ReadFromFullInt <= '1';
    END IF;

    IF RCLK'event AND RCLK = '1'  THEN

        IF RTNeg = '0' THEN
            IF RENNeg = '1' AND WENNeg = '1' THEN
                EmptyFlagInt <= '0';
                RTBeginInt <= '1';
                RDPointerInt <= 0;
            END IF;
        ELSIF RTEndInt = '1' THEN
            RTBeginInt <= '0';
            EmptyFlagInt <= '1';