idt72271.vhd

VHDL的ram和fifo model code 包含众多的厂家

                    SetupLow        => tsetup_FWFTSI_MRSNeg_noedge_negedge,
                    CheckEnabled    => True,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_FWFTSI_MRSNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_FWFTSI_MRSNeg);

              END IF;

              --25 FWFTSI_MRSNeg setup time check (tRSR)

              IF FWFTSI'event OR (MRSNeg'event AND MRSNeg = '1') THEN

                VitalSetupHoldCheck (
                    TestSignal      => FWFTSI,
                    TestSignalName  => "FWFTSI",
                    RefSignal       => MRSNeg,
                    RefSignalName   => "MRSNeg",
                    HoldHigh        => thold_FWFTSI_MRSNeg_noedge_posedge,
                    HoldLow         => thold_FWFTSI_MRSNeg_noedge_posedge,
                    CheckEnabled    => True,
                    RefTransition   => '\',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_FWFTSI_MRSNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_FWFTSI_MRSNeg);

              END IF;

                Violation :=

                    Pviol_WCLK            OR
                    Pviol_RCLK            OR
                    Pviol_MRSNeg          OR
                    Pviol_PRSNeg          OR
                    Tviol_D0_WCLK         OR
                    Tviol_WENNeg_WCLK     OR
                    Tviol_SENNeg_WCLK     OR
                    Tviol_RENNeg_RCLK     OR
                    Tviol_RTNeg_RCLK      OR
                    Tviol_LDNeg_WCLK      OR
                    Tviol_LDNeg_RCLK      OR
                    Tviol_WENNeg_MRSNeg   OR
                    Tviol_RENNeg_MRSNeg   OR
                    Tviol_LDNeg_MRSNeg    OR
                    Tviol_RTNeg_MRSNeg    OR
                    Tviol_SENNeg_MRSNeg   OR
                    Tviol_WENNeg_PRSNeg   OR
                    Tviol_RENNeg_PRSNeg   OR
                    Tviol_RTNeg_PRSNeg    OR
                    Tviol_SENNeg_PRSNeg   OR
                    Tviol_FWFTSI_WCLK     OR
                    Tviol_FWFTSI_MRSNeg   OR
                    Tviol_WENNeg_RCLK;

                ASSERT   Violation = '0'
                REPORT   InstancePath & partID & " : signal values may be" &
                         " incorret due timing violation(s)"
                SEVERITY Warning;

            END IF;

        END PROCESS TimingChecks;

        ------------------------------------------------------------------------
        -- Functionality section                                              --
        ------------------------------------------------------------------------

IDT: BLOCK
port(D0                : IN std_ulogic := 'X';
     D1                : IN std_ulogic := 'X';
     D2                : IN std_ulogic := 'X';
     D3                : IN std_ulogic := 'X';
     D4                : IN std_ulogic := 'X';
     D5                : IN std_ulogic := 'X';
     D6                : IN std_ulogic := 'X';
     D7                : IN std_ulogic := 'X';
     D8                : IN std_ulogic := 'X';
     MRSNeg            : IN std_ulogic := 'X';
     PRSNeg            : IN std_ulogic := 'X';
     RTNeg             : IN std_ulogic := 'X';
     FWFTSI            : IN std_ulogic := 'X';
     WCLK              : IN std_ulogic := 'X';
     WENNeg            : IN std_ulogic := 'X';
     RENNeg            : IN std_ulogic := 'X';
     RCLK              : IN std_ulogic := 'X';
     OENeg             : IN std_ulogic := 'X';
     SENNeg            : IN std_ulogic := 'X';
     LDNeg             : IN std_ulogic := 'X';
     FS                : IN std_ulogic := 'X';
     FFIRNeg           : OUT std_ulogic := 'U';
     EFORNeg           : OUT std_ulogic := 'U';
     PAFNeg            : OUT std_ulogic := 'U';
     PAENeg            : OUT std_ulogic := 'U';
     HFNeg             : OUT std_ulogic := 'U';
     Q0                : OUT std_ulogic := 'U';
     Q1                : OUT std_ulogic := 'U';
     Q2                : OUT std_ulogic := 'U';
     Q3                : OUT std_ulogic := 'U';
     Q4                : OUT std_ulogic := 'U';
     Q5                : OUT std_ulogic := 'U';
     Q6                : OUT std_ulogic := 'U';
     Q7                : OUT std_ulogic := 'U';
     Q8                : OUT std_ulogic := 'U'
);

port map (
          MRSNeg     => MRSNeg,
          D0         => D(0),
          D1         => D(1),
          D2         => D(2),
          D3         => D(3),
          D4         => D(4),
          D5         => D(5),
          D6         => D(6),
          D7         => D(7),
          D8         => D(8),
          Q0         => Q_zd(0),
          Q1         => Q_zd(1),
          Q2         => Q_zd(2),
          Q3         => Q_zd(3),
          Q4         => Q_zd(4),
          Q5         => Q_zd(5),
          Q6         => Q_zd(6),
          Q7         => Q_zd(7),
          Q8         => Q_zd(8),
          RCLK       => RCLK,
          PRSNeg     => PRSNeg,
          RTNeg      => RTNeg,
          FWFTSI     => FWFTSI,
          WCLK       => WCLK,
          RENNeg     => RENNeg,
          WENNeg     => WENNeg,
          OENeg      => OENeg,
          SENNeg     => SENNeg,
          LDNeg      => LDNeg,
          FS         => FS,
          FFIRNeg    => FFIRNeg_zd,
          EFORNeg    => EFORNeg_zd,
          HFNeg      => HFNeg_zd,
          PAENeg     => PAENeg_zd,
          PAFNeg     => PAFNeg_zd);

CONSTANT cond1           :  integer:= 127;
CONSTANT cond2           :  integer:= 1023;
CONSTANT LSBS            :  integer:= 7;
CONSTANT MSBS            :  integer:= 6;
CONSTANT FIFOsize        :  integer := 32768;

SIGNAL FullFlagInt       :  std_logic;
SIGNAL InputReadyInt     :  std_logic;
SIGNAL EmptyFlagInt      :  std_logic;
SIGNAL OutputReadyInt    :  std_logic;

SIGNAL DataInInt         :  std_logic_vector(8 DOWNTO 0);
SIGNAL DataOutInt        :  std_logic_vector(8 DOWNTO 0);

SIGNAL WRPointerInt      :  integer RANGE FIFOSize DOWNTO 0;
SIGNAL RDPointerInt      :  integer RANGE FIFOSize DOWNTO 0;

SIGNAL WRIntoEmptyInt    :  std_logic;

SIGNAL DiffInt           :  integer RANGE FIFOSize DOWNTO 0;
SIGNAL PrevDiffInt:         integer RANGE FIFOSize DOWNTO 0;

SIGNAL AlmostEmptyCondInt:  integer RANGE FIFOSize DOWNTO 0;
SIGNAL AlmostFullCondInt :  integer RANGE FIFOSize DOWNTO 0;
SIGNAL HalfFullCondInt   :  integer RANGE FIFOSize DOWNTO 0;

SIGNAL InternalClockInt  :  std_logic;
SIGNAL ReadFromFullInt   :  std_logic;
SIGNAL OutputRegisterInt :  std_logic_vector(8 DOWNTO 0);

SIGNAL AEFInt            :  std_logic;
SIGNAL PAE1Int           :  std_logic;
SIGNAL PAE2Int           :  std_logic;
SIGNAL FullFlag1Int      :  std_logic;
SIGNAL HalfFull1Int      :  std_logic;

SIGNAL AFFInt            :  std_logic;
SIGNAL RTAFFInt          :  std_logic;
SIGNAL PAF1Int           :  std_logic;
SIGNAL PAF2Int           :  std_logic;

SIGNAL LSBPAEInt         :  std_logic_vector(LSBS DOWNTO 0);
SIGNAL MSBPAEInt         :  std_logic_vector(MSBS DOWNTO 0);
SIGNAL LSBPAFInt         :  std_logic_vector(LSBS DOWNTO 0);
SIGNAL MSBPAFInt         :  std_logic_vector(MSBS DOWNTO 0);
SIGNAL LSBPAE1Int        :  std_logic_vector(LSBS DOWNTO 0);
SIGNAL MSBPAE1Int        :  std_logic_vector(MSBS DOWNTO 0);
SIGNAL LSBPAF1Int        :  std_logic_vector(LSBS DOWNTO 0);
SIGNAL MSBPAF1Int        :  std_logic_vector(MSBS DOWNTO 0);
SIGNAL FrontNumInt       :  std_logic_vector(4 DOWNTO 0);
SIGNAL ProgFinishedInt   :  std_logic;
SIGNAL ParProgInt        :  std_logic;
SIGNAL SerialRegInt      :  std_logic_vector
                              (MSBS + LSBS + MSBS+LSBS + 3 DOWNTO 0);
SIGNAL ReadFnInt         :  std_logic_vector(1 DOWNTO 0);
SIGNAL OutputValidInt    :  std_logic;
SIGNAL ModeInt           :  std_logic;
SIGNAL RTBeginInt        :  std_logic;
SIGNAL RTEndInt          :  std_logic;
SIGNAL RTExtraInt        :  std_logic;
SIGNAL AfterRTInt        :  std_logic;
SIGNAL AEDisableAfterRTInt: std_logic;
SIGNAL AfterRTSkew2Int   :  std_logic;
SIGNAL EmptyRecovExtraInt:  std_logic;
SIGNAL EmptyRecovInt     :  std_logic;
SIGNAL WrEnInt           :  std_logic;
SIGNAL RdEnInt           :  std_logic;
SIGNAL FFIRint           :  std_logic;
SIGNAL EFORint           :  std_logic;
SIGNAL FirstWordWritedInt:  std_logic;
SIGNAL ReadFirstAfterRTInt: std_logic;
SIGNAL InpRegInt         :  std_logic_vector(8 DOWNTO 0);
SIGNAL IDTFirstWordInt   :  std_logic;
SIGNAL FWFTFirstWordInt  :  std_logic;
SIGNAL SerialInputInt    :  std_logic;
SIGNAL PAFInt            :  std_logic;
SIGNAL PAEInt            :  std_logic;
SIGNAL HFInt             :  std_logic;

SIGNAL VirtualWRAEF      :  std_logic;
SIGNAL VirtualWRAFF      :  std_logic;
SIGNAL PAEEnable         :  std_logic;
SIGNAL PAFEnable         :  std_logic;
SIGNAL PafenDop          :  std_logic;
SIGNAL PaeenDop          :  std_logic;
SIGNAL PaeenDop1         :  std_logic;

BEGIN

SerialInputInt <= FWFTSI;
InputReadyInt <= not FullFlagInt;

PAFNeg <= PAFInt when PAFEnable = '1' else
          'U'    when PAFEnable = 'U' else
          'X';

PAENeg <= PAEInt when PAEEnable = '1' else
          'U'    when PAEEnable = 'U' else
          'X';

HFNeg  <= HFInt;
FFIRNeg <= FFIRint;
EFORNeg <= EFORint;

FFIRint <= FullFlagInt WHEN ModeInt = '0' ELSE
           InputReadyInt;
EFORint <= EmptyFlagInt WHEN ModeInt = '0' ELSE
           OutputReadyInt;

WrEnInt <= '1' WHEN RTBeginInt = '0' AND
                    ((FullFlagInt = '1' AND ModeInt = '0') OR
                    (InputReadyInt = '0' AND ModeInt = '1')) ELSE
           '0';

RdEnInt <= '1' WHEN (EmptyFlagInt = '1' AND ModeInt = '0') or
                    (OutputReadyInt = '0' AND ModeInt = '1'
                    AND DiffInt > 0) ELSE
           '0';

InternalClockInt <= RCLK WHEN FS = '0' ELSE
                    WCLK;

DataInInt <= D8 & D7 & D6 & D5 & D4 & D3 & D2 & D1& D0;

Q0 <= DataOutInt(0);
Q1 <= DataOutInt(1);
Q2 <= DataOutInt(2);
Q3 <= DataOutInt(3);
Q4 <= DataOutInt(4);
Q5 <= DataOutInt(5);
Q6 <= DataOutInt(6);
Q7 <= DataOutInt(7);
Q8 <= DataOutInt(8);

LSBPAE1Int <= SerialRegInt(LSBS DOWNTO 0);
MSBPAE1Int <= SerialRegInt(MSBS+LSBS+1 DOWNTO LSBS+1);
LSBPAF1Int <= SerialRegInt(LSBS + MSBS + LSBS + 2 DOWNTO MSBS+LSBS+2);
MSBPAF1Int <= SerialRegInt(MSBS + LSBS + MSBS + LSBS + 3 DOWNTO
                      LSBS + MSBS+LSBS + 3);

Outp_ready:PROCESS(EmptyFlagInt, RCLK)
BEGIN
IF EmptyFlagInt = '1' and RTNeg = '1' THEN
    OutputReadyInt <= '0';
ELSIF RCLK'event AND RCLK = '1' THEN
    IF RTNeg = '0' OR (EmptyFlagInt = '0' AND DiffInt = 0) THEN
        OutputReadyInt <= '1' ;
    END IF;
END IF;
END PROCESS;

AEFEN:PROCESS(RCLK)
BEGIN
IF RCLK'event AND RCLK = '1' THEN
    IF VirtualWRAEF = '1' THEN
        PaeenDop1 <= '1';
    END IF;
    IF PaeenDop1 = '1' THEN
        PaeenDop1 <= '0';
        PaeenDop <= '1';
    END IF;
    IF PaeenDop = '1' AND VirtualWRAEF = '0' THEN
        PaeenDop <= '0';
    END IF;
END IF;
END PROCESS;

Offset_loading: PROCESS(WCLK, MRSNeg, PaeenDop)
BEGIN
IF MRSNeg = '0' THEN
    PAEEnable <= '1';
    PAFEnable <= '1';
    FrontNumInt <= "00000";
    ProgFinishedInt <= '0';
    HalfFullCondInt <= (FIFOSize) / 2;
    IF LDNeg ='1' THEN
        AlmostEmptyCondInt <= cond2;
        AlmostFullCondInt <= FIFOSize - cond2;
        ParProgInt <= '0';
        LSBPAEInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond2, LSBS+1));
        LSBPAFInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond2, LSBS+1));
        MSBPAEInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(1, MSBS+1));
        MSBPAFInt(MSBS DOWNTO 0) <= std_logic_vector(to_slv(1, MSBS+1));

        SerialRegInt(LSBS DOWNTO 0) <= std_logic_vector(to_slv(cond1, LSBS+1));
        SerialRegInt(LSBS+MSBS+LSBS+2 DOWNTO MSBS+LSBS+2) <=
                     std_logic_vector(to_slv(cond1, LSBS+1));
        SerialRegInt(MSBS+LSBS+1 DOWNTO LSBS+1) <=
                     std_logic_vector(to_slv(1, MSBS+1));
        SerialRegInt(MSBS+LSBS+MSBS+LSBS+3 DOWNTO LSBS+MSBS+LSBS+3) <=