📄 idt72271.vhd
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XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_WCLK); END IF; --8 RENNeg/RCLK setup/hold time check (tENS, tENH) IF RENNeg'event OR (RCLK'event AND RCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RENNeg_RCLK_noedge_posedge, HoldHigh => thold_RENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK); END IF; --9 RTNeg/RCLK setup/hold time check (tENS, tENH) IF RTNeg'event OR (RCLK'event AND RCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_RTNeg_RCLK_noedge_posedge, HoldHigh => thold_RTNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_RCLK); END IF; --10 WENNeg/RTNeg/RCLK setup time check (tRTS) IF WENNeg'event OR ((RCLK'event AND RCLK = '1') AND RTNeg = '0') THEN VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupHigh => tsetup_WENNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_RCLK); END IF; --12 LDNeg/WCLK setup/hold time check (tLDS/tLDH) IF LDNeg'event OR ((WCLK'event AND WCLK = '1') AND (WENNeg ='0' OR SENNeg ='0')) THEN VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => WCLK, RefSignalName => "WCLK", SetupLow => tsetup_LDNeg_WCLK_noedge_posedge, HoldHigh => thold_LDNeg_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_WCLK); END IF; --13 LDNeg/RCLK setup/hold time check (tLDS/tLDH) IF LDNeg'event OR ((RCLK'event AND RCLK = '1') AND (RENNeg = '0')) THEN VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => RCLK, RefSignalName => "RCLK", SetupLow => tsetup_LDNeg_RCLK_noedge_posedge, HoldHigh => thold_LDNeg_RCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RCLK); END IF; END IF; --14 RENNeg/MRSNeg setup/recovery time check (tRSS/tRSR) IF RENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg_noedge_posedge, HoldLow => thold_RENNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg); END IF; --15 WENNeg/MRSNeg setup/recovery time check (tRSS/tRSR) IF WENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_WENNeg_MRSNeg_noedge_posedge, HoldLow => thold_WENNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg); END IF; --16 LDNeg/MRSNeg setup/recovery time check (tRSS/tRSR) IF LDNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => LDNeg, TestSignalName => "LDNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_LDNeg_MRSNeg_noedge_posedge, SetupLow => tsetup_LDNeg_MRSNeg_noedge_posedge, HoldHigh => thold_LDNeg_MRSNeg_noedge_posedge, HoldLow => thold_LDNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_LDNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_MRSNeg); END IF; --17 RTNeg/MRSNeg setup time check (tRSS) IF RTNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_RTNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_MRSNeg); END IF; --18 SENNeg/MRSNeg setup time check (tRSS) IF SENNeg'event OR (MRSNeg'event AND MRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_SENNeg_MRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg); END IF; --19 RENNeg/PRSNeg setup/recovery time check (tRSS/tRSR) IF RENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RENNeg, TestSignalName => "RENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_RENNeg_PRSNeg_noedge_posedge, HoldLow => thold_RENNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_PRSNeg); END IF; --20 WENNeg/PRSNeg setup/recovery time check (tRSS/tRSR) IF WENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => WENNeg, TestSignalName => "WENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_WENNeg_PRSNeg_noedge_posedge, HoldLow => thold_WENNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_WENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_PRSNeg); END IF; --21 RTNeg/PRSNeg setup time check (tRSS) IF RTNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => RTNeg, TestSignalName => "RTNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_RTNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RTNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_PRSNeg); END IF; --22 SENNeg/PRSNeg setup time check (tRSS) IF SENNeg'event OR (PRSNeg'event AND PRSNeg = '1') THEN VitalSetupHoldCheck ( TestSignal => SENNeg, TestSignalName => "SENNeg", RefSignal => PRSNeg, RefSignalName => "PRSNeg", SetupHigh => tsetup_SENNeg_PRSNeg_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SENNeg_PRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_PRSNeg); END IF; --23 FWFTSI/WCLK setup time check (tDS) IF (FWFTSI'event AND SENNeg = '0' AND LDNeg = '0') OR (WCLK'event AND WCLK = '1') THEN VitalSetupHoldCheck ( TestSignal => FWFTSI, TestSignalName => "FWFTSI", RefSignal => WCLK, RefSignalName => "WCLK", SetupHigh => tsetup_FWFTSI_WCLK_noedge_posedge, SetupLow => tsetup_FWFTSI_WCLK_noedge_posedge, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FWFTSI_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FWFTSI_WCLK); END IF; --24 FWFTSI_MRSNeg setup time check (tFWFT) IF FWFTSI'event OR (MRSNeg'event AND MRSNeg = '0') THEN VitalSetupHoldCheck ( TestSignal => FWFTSI, TestSignalName => "FWFTSI", RefSignal => MRSNeg, RefSignalName => "MRSNeg", SetupHigh => tsetup_FWFTSI_MRSNeg_noedge_negedge,⌨️ 快捷键说明
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