📄 idt723636.vhd

📁 VHDL的ram和fifo model code 包含众多的厂家
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---------------------------------------------------------------------------------- File name : idt723636.vhd---------------------------------------------------------------------------------  Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/--  Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT--  and supported by Free Model Foundry; http://www.FreeModelFoundry.com----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License version 2 as--  published by the Free Software Foundation.----  This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no--  warranty with respect to the information contained herein. IDT DISCLAIMS--  AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING--  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE--  ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN--  NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN--  CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,--  CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR--  APPLICATION OF THE VHDL model. Further, IDT reserves the right to make--  changes without notice to any product herein to improve reliability,--  function, or design.  IDT does not convey any license under patent rights--  or any other intellectual property rights, including those of third parties.--  IDT is not obligated to provide maintenance or support for the licensed VHDL--  model.---- MODIFICATION HISTORY :---- version | author            | mod date  | changes made--   V1.0  | Anatoli Sokhatski | 98 APR 14 | initial coding--   V1.1  | R. Munden  | 02 MAY 19 | licensing changed to GPL----------------------------------------------------------------------------------- PART DESCRIPTION :---- Library:     IDT_FIFO-- Technology:  CMOS-- Part:        IDT723636---- Descripton:  Triple Bus SyncFIFO With Bus-Matching 512x36x2--------------------------------------------------------------------------------LIBRARY ieee;   USE ieee.std_logic_1164.ALL;                USE ieee.std_logic_arith.ALL;                USE ieee.vital_primitives.ALL;                USE ieee.vital_timing.ALL;LIBRARY fmf;    USE fmf.ff_package.ALL;                USE fmf.gen_utils.ALL;                USE fmf.conversions.to_nat;                ---------------------------------------------------------------------------------- ENTITY DECLARATION                                                         ----------------------------------------------------------------------------------ENTITY IDT723636 IS    GENERIC (    -----------------------------------------------------------------------------    -- VITAL generics    -----------------------------------------------------------------------------        -- tipd delays: interconnect path delays    --              (there must be one generic for each input pin)    tipd_A0       : VitalDelayType01 := VitalZeroDelay01;    tipd_A1       : VitalDelayType01 := VitalZeroDelay01;    tipd_A2       : VitalDelayType01 := VitalZeroDelay01;    tipd_A3       : VitalDelayType01 := VitalZeroDelay01;    tipd_A4       : VitalDelayType01 := VitalZeroDelay01;    tipd_A5       : VitalDelayType01 := VitalZeroDelay01;    tipd_A6       : VitalDelayType01 := VitalZeroDelay01;    tipd_A7       : VitalDelayType01 := VitalZeroDelay01;    tipd_A8       : VitalDelayType01 := VitalZeroDelay01;    tipd_A9       : VitalDelayType01 := VitalZeroDelay01;    tipd_A10      : VitalDelayType01 := VitalZeroDelay01;    tipd_A11      : VitalDelayType01 := VitalZeroDelay01;    tipd_A12      : VitalDelayType01 := VitalZeroDelay01;    tipd_A13      : VitalDelayType01 := VitalZeroDelay01;    tipd_A14      : VitalDelayType01 := VitalZeroDelay01;    tipd_A15      : VitalDelayType01 := VitalZeroDelay01;    tipd_A16      : VitalDelayType01 := VitalZeroDelay01;    tipd_A17      : VitalDelayType01 := VitalZeroDelay01;    tipd_A18      : VitalDelayType01 := VitalZeroDelay01;    tipd_A19      : VitalDelayType01 := VitalZeroDelay01;    tipd_A20      : VitalDelayType01 := VitalZeroDelay01;    tipd_A21      : VitalDelayType01 := VitalZeroDelay01;    tipd_A22      : VitalDelayType01 := VitalZeroDelay01;    tipd_A23      : VitalDelayType01 := VitalZeroDelay01;    tipd_A24      : VitalDelayType01 := VitalZeroDelay01;    tipd_A25      : VitalDelayType01 := VitalZeroDelay01;    tipd_A26      : VitalDelayType01 := VitalZeroDelay01;    tipd_A27      : VitalDelayType01 := VitalZeroDelay01;    tipd_A28      : VitalDelayType01 := VitalZeroDelay01;    tipd_A29      : VitalDelayType01 := VitalZeroDelay01;    tipd_A30      : VitalDelayType01 := VitalZeroDelay01;    tipd_A31      : VitalDelayType01 := VitalZeroDelay01;    tipd_A32      : VitalDelayType01 := VitalZeroDelay01;    tipd_A33      : VitalDelayType01 := VitalZeroDelay01;    tipd_A34      : VitalDelayType01 := VitalZeroDelay01;    tipd_A35      : VitalDelayType01 := VitalZeroDelay01;    tipd_BEFWFT   : VitalDelayType01 := VitalZeroDelay01;    tipd_C0       : VitalDelayType01 := VitalZeroDelay01;    tipd_C1       : VitalDelayType01 := VitalZeroDelay01;    tipd_C2       : VitalDelayType01 := VitalZeroDelay01;    tipd_C3       : VitalDelayType01 := VitalZeroDelay01;    tipd_C4       : VitalDelayType01 := VitalZeroDelay01;    tipd_C5       : VitalDelayType01 := VitalZeroDelay01;    tipd_C6       : VitalDelayType01 := VitalZeroDelay01;    tipd_C7       : VitalDelayType01 := VitalZeroDelay01;    tipd_C8       : VitalDelayType01 := VitalZeroDelay01;    tipd_C9       : VitalDelayType01 := VitalZeroDelay01;    tipd_C10      : VitalDelayType01 := VitalZeroDelay01;    tipd_C11      : VitalDelayType01 := VitalZeroDelay01;    tipd_C12      : VitalDelayType01 := VitalZeroDelay01;    tipd_C13      : VitalDelayType01 := VitalZeroDelay01;    tipd_C14      : VitalDelayType01 := VitalZeroDelay01;    tipd_C15      : VitalDelayType01 := VitalZeroDelay01;    tipd_C16      : VitalDelayType01 := VitalZeroDelay01;    tipd_C17      : VitalDelayType01 := VitalZeroDelay01;    tipd_CLKA     : VitalDelayType01 := VitalZeroDelay01;    tipd_CLKB     : VitalDelayType01 := VitalZeroDelay01;    tipd_CLKC     : VitalDelayType01 := VitalZeroDelay01;    tipd_CSANeg   : VitalDelayType01 := VitalZeroDelay01;    tipd_CSBNeg   : VitalDelayType01 := VitalZeroDelay01;    tipd_ENA      : VitalDelayType01 := VitalZeroDelay01;    tipd_FS0SD    : VitalDelayType01 := VitalZeroDelay01;    tipd_FS1SEN   : VitalDelayType01 := VitalZeroDelay01;    tipd_MBA      : VitalDelayType01 := VitalZeroDelay01;    tipd_MBB      : VitalDelayType01 := VitalZeroDelay01;    tipd_MBC      : VitalDelayType01 := VitalZeroDelay01;    tipd_MRS1Neg  : VitalDelayType01 := VitalZeroDelay01;    tipd_MRS2Neg  : VitalDelayType01 := VitalZeroDelay01;    tipd_PRS1Neg  : VitalDelayType01 := VitalZeroDelay01;    tipd_PRS2Neg  : VitalDelayType01 := VitalZeroDelay01;    tipd_RENB     : VitalDelayType01 := VitalZeroDelay01;    tipd_SIZEB    : VitalDelayType01 := VitalZeroDelay01;    tipd_SIZEC    : VitalDelayType01 := VitalZeroDelay01;    tipd_SPMNeg   : VitalDelayType01 := VitalZeroDelay01;    tipd_WRA      : VitalDelayType01 := VitalZeroDelay01;    tipd_WENC     : VitalDelayType01 := VitalZeroDelay01;        -- tpd delays: propagation delays    -- tA    tpd_CLKA_A0                             : VitalDelayType01 := UnitDelay01;    -- tWFF    tpd_CLKA_FFAIRA                         : VitalDelayType01 := UnitDelay01;    -- tREF    tpd_CLKA_EFAORA                         : VitalDelayType01 := UnitDelay01;    -- tPAE    tpd_CLKA_AEANeg                         : VitalDelayType01 := UnitDelay01;    -- tPAF    tpd_CLKA_AFANeg                         : VitalDelayType01 := UnitDelay01;    -- tPMF    tpd_CLKA_MBF1Neg                        : VitalDelayType01 := UnitDelay01;    -- tPMR    tpd_CLKA_B0                             : VitalDelayType01 := UnitDelay01;    -- tMDV    tpd_MBA_A0                              : VitalDelayType01 := UnitDelay01;    -- tRSF    tpd_MRS1Neg_AEBNeg                      : VitalDelayType01 := UnitDelay01;    -- tEN/tDIS    tpd_CSANeg_A0                           : VitalDelayType01Z := UnitDelay01Z;    -- tpw values: pulse widths    -- tCLK    tperiod_CLKA_posedge                    : VitalDelayType := UnitDelay;    -- tCLKH    -- tCLKL    tpw_CLKA_posedge                        : VitalDelayType := UnitDelay;    tpw_CLKA_negedge                        : VitalDelayType := UnitDelay;    -- tsetup values: setup times    -- tDS    tsetup_A0_CLKA                          : VitalDelayType := UnitDelay;    -- tENS    tsetup_CSANeg_CLKA                      : VitalDelayType := UnitDelay;    -- tRSTS    tsetup_MRS1Neg_CLKA                     : VitalDelayType := UnitDelay;    -- tFSS    tsetup_FS0SD_MRS1Neg                    : VitalDelayType := UnitDelay;    -- tBES    tsetup_BEFWFT_MRS1Neg                   : VitalDelayType := UnitDelay;    -- tSPMS    tsetup_SPMNeg_MRS1Neg                   : VitalDelayType := UnitDelay;    -- tSDS    tsetup_FS0SD_CLKA                       : VitalDelayType := UnitDelay;    -- tSENS    tsetup_FS1SEN_CLKA                      : VitalDelayType := UnitDelay;    -- tFWS    tsetup_BEFWFT_CLKA                      : VitalDelayType := UnitDelay;    -- thold values: hold times    -- tDH    thold_A0_CLKA                           : VitalDelayType := UnitDelay;    -- tENH    thold_CSANeg_CLKA                       : VitalDelayType := UnitDelay;    -- tRSTH    thold_MRS1Neg_CLKA                      : VitalDelayType := UnitDelay;    -- tFSH    thold_FS0SD_MRS1Neg                     : VitalDelayType := UnitDelay;    -- tBEH    thold_BEFWFT_MRS1Neg                    : VitalDelayType := UnitDelay;    -- tSPMH    thold_SPMNeg_MRS1Neg                    : VitalDelayType := UnitDelay;    -- tSDH    thold_FS0SD_CLKA                        : VitalDelayType := UnitDelay;    -- tSENH    thold_FS1SEN_CLKA                       : VitalDelayType := UnitDelay;    -- tSPH    thold_FS1SEN_MRS1Neg                    : VitalDelayType := UnitDelay;        -- tskew values: skew times        tdevice_SKEW1        : VitalDelayType := UnitDelay;    -- Skew Time, between posedge CLKA and posedge CLKB for EFBNeg and FFANeg;    --		  between posedge CLKC and posedge CLKA for EFANeg and FFCIRC;    tdevice_SKEW2        : VitalDelayType := UnitDelay;    -- Skew Time, between posedge CLKA and posedge CLKB for AFBNeg and AFANeg;    --		  between posedge CLKC and posedge CLKA for AFANeg and AFCNeg;        -- generic control parameters    InstancePath   : STRING  := DefaultInstancePath;    TimingChecksOn : BOOLEAN := DefaultTimingChecks;    MsgOn          : BOOLEAN := DefaultMsgOn;    XOn            : BOOLEAN := DefaultXOn;    TimingModel    : STRING  := DefaultTimingModel          );  PORT (    A0       : INOUT std_logic; -----------------------------    A1       : INOUT std_logic; --    A2       : INOUT std_logic; --    A3       : INOUT std_logic; --    A4       : INOUT std_logic; --    A5       : INOUT std_logic; --    A6       : INOUT std_logic; --    A7       : INOUT std_logic; --    A8       : INOUT std_logic; --    A9       : INOUT std_logic; --    A10      : INOUT std_logic; --    A11      : INOUT std_logic; --    A12      : INOUT std_logic; --    A13      : INOUT std_logic; --    A14      : INOUT std_logic; --    A15      : INOUT std_logic; --    A16      : INOUT std_logic; --    A17      : INOUT std_logic; --    A18      : INOUT std_logic; -- 36 pin bidirectional Port-A data bus    A19      : INOUT std_logic; --    A20      : INOUT std_logic; --    A21      : INOUT std_logic; --    A22      : INOUT std_logic; --    A23      : INOUT std_logic; --    A24      : INOUT std_logic; --    A25      : INOUT std_logic; --    A26      : INOUT std_logic; --    A27      : INOUT std_logic; --    A28      : INOUT std_logic; --    A29      : INOUT std_logic; --    A30      : INOUT std_logic; --    A31      : INOUT std_logic; --    A32      : INOUT std_logic; --    A33      : INOUT std_logic; --    A34      : INOUT std_logic; --    A35      : INOUT std_logic; --------------------------------------    AEANeg   : OUT   std_logic := 'U'; -- Almost-Empty Flag for Port-A    AEBNeg   : OUT   std_logic := 'U'; -- Almost-Empty Flag for Port-B    AFANeg   : OUT   std_logic := 'U'; -- Almost-Full Flag for Port-A    AFCNeg   : OUT   std_logic := 'U'; -- Almost-Full Flag for Port-C    B0       : OUT std_logic; --------------------------------------    B1       : OUT std_logic; --    B2       : OUT std_logic; --    B3       : OUT std_logic; --    B4       : OUT std_logic; --    B5       : OUT std_logic; --    B6       : OUT std_logic; --    B7       : OUT std_logic; -- 18 pin output Port-B data bus    B8       : OUT std_logic; --    B9       : OUT std_logic; --    B10      : OUT std_logic; --    B11      : OUT std_logic; --    B12      : OUT std_logic; --    B13      : OUT std_logic; --    B14      : OUT std_logic; --    B15      : OUT std_logic; --    B16      : OUT std_logic; --    B17      : OUT std_logic; --------------------------------------------    BEFWFT   : IN std_logic; -- Big Endian / First Word Fall Through Select	    C0       : IN std_logic; ---------------------------------------------    C1       : IN std_logic; --    C2       : IN std_logic; --    C3       : IN std_logic; --    C4       : IN std_logic; --    C5       : IN std_logic; --    C6       : IN std_logic; --    C7       : IN std_logic; -- 18 pin input Port-C data bus    C8       : IN std_logic; --    C9       : IN std_logic; --    C10      : IN std_logic; --    C11      : IN std_logic; --    C12      : IN std_logic; --    C13      : IN std_logic; --    C14      : IN std_logic; --    C15      : IN std_logic; --    C16      : IN std_logic; --    C17      : IN std_logic; -----------------------------    CLKA     : IN    std_logic := 'X'; -- Port-A clock    CLKB     : IN    std_logic := 'X'; -- Port-B clock    CLKC     : IN    std_logic := 'X'; -- Port-B clock    CSANeg   : IN    std_logic := 'X'; -- Port-A Chip Select    CSBNeg   : IN    std_logic := 'X'; -- Port-B Chip Select    EFAORA   : OUT   std_logic := 'U'; -- Port-A Empty / Output Ready Flag    EFBORB   : OUT   std_logic := 'U'; -- Port-B Empty / Output Ready Flag    ENA      : IN    std_logic := 'X'; -- Port-A Enable    FFAIRA   : OUT   std_logic := 'U'; -- Port-A Full / Input Ready Flag    FFCIRC   : OUT   std_logic := 'U'; -- Port-A Full / Input Ready Flag    FS0SD    : IN    std_logic := 'X'; -- Flag Offset Select 0 / Serial Data     FS1SEN   : IN    std_logic := 'X'; -- Flag Offset Select 1 / Serial Enable    MBA      : IN    std_logic := 'X'; -- Port-A Mailbox Select    MBB      : IN    std_logic := 'X'; -- Port-B Mailbox Select    MBC      : IN    std_logic := 'X'; -- Port-C Mailbox Select    MBF1Neg  : OUT   std_logic := 'U'; -- Mail1 Register Flag    MBF2Neg  : OUT   std_logic := 'U'; -- Mail2 Register Flag    MRS1Neg  : IN    std_logic := 'X'; -- Master Reset    MRS2Neg  : IN    std_logic := 'X'; -- Master Reset    PRS1Neg  : IN    std_logic := 'X'; -- Partial Reset    PRS2Neg  : IN    std_logic := 'X'; -- Partial Reset    RENB     : IN    std_logic := 'X'; -- Port-B Read Enable    SIZEB    : IN    std_logic := 'X'; -- Port-B Bus Size Select    SIZEC    : IN    std_logic := 'X'; -- Port-C Bus Size Select    SPMNeg   : IN    std_logic := 'X'; -- Serial Programming    WENC     : IN    std_logic := 'X'; -- Port-C Write Enable
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