idt72v821.ftm
来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 111 行
FTM
111 行
<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT72V821 Parts</TITLE><REVISION.HISTORY>version: | author: | mod date: | changes made: V1.0 R. Munden 99 JUN 24 Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT72V821<FMFTIME>IDT72V821L10TF<SOURCE>IDT data sheet January 1999</SOURCE>IDT72V821L10PF<SOURCE>IDT data sheet January 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RSNeg EFNeg (2:7:10) (2:7:10)) (IOPATH RCLK EFNeg (2:4:6.5) (2:4:6.5)) (IOPATH RCLK PAENeg (2:4:6.5) (2:4:6.5)) (IOPATH WCLK FFNeg (2:4:6.5) (2:4:6.5)) (IOPATH WCLK PAFNeg (2:4:6.5) (2:4:6.5)) (IOPATH RSNeg Q0 (2:7:10) (2:7:10) (2:7:10) (2:7:10) (2:7:10) (2:7:10)) (IOPATH RCLK Q0 (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5)) (IOPATH OENeg Q0 (3:4:6) (3:4:6) (3:4:6) (0:4:6) (3:4:6) (0:4:6)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (10)) (PERIOD (posedge WCLK) (10)) (WIDTH (posedge RCLK) (4.5)) (WIDTH (negedge RCLK) (4.5)) (WIDTH (posedge WCLK) (4.5)) (WIDTH (negedge RSNeg) (10)) (SETUPHOLD D0 WCLK (3) (0.5)) (SETUPHOLD REN1Neg RCLK (3) (0.5)) (SETUP REN1Neg RSNeg (8)) (RECOVERY REN1Neg RSNeg (8)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (5) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (14) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72V821L15TF<SOURCE>IDT data sheet January 1999</SOURCE>IDT72V821L15PF<SOURCE>IDT data sheet January 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RSNeg EFNeg (3:10:15) (3:10:15)) (IOPATH RCLK EFNeg (2:6:10) (2:6:10)) (IOPATH RCLK PAENeg (2:6:10) (2:6:10)) (IOPATH WCLK FFNeg (2:6:10) (2:6:10)) (IOPATH WCLK PAFNeg (2:6:10) (2:6:10)) (IOPATH RSNeg Q0 (3:10:15) (3:10:15) (3:10:15) (3:10:15) (3:10:15) (3:10:15)) (IOPATH RCLK Q0 (2:6:10) (2:6:10) (2:6:10) (2:6:10) (2:6:10) (2:6:10)) (IOPATH OENeg Q0 (3:6:8) (3:6:8) (3:6:8) (0:6:8) (3:6:8) (0:6:8)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (15)) (PERIOD (posedge WCLK) (15)) (WIDTH (posedge RCLK) (6)) (WIDTH (negedge RCLK) (6)) (WIDTH (negedge RSNeg) (15)) (SETUPHOLD D0 WCLK (4) (1)) (SETUPHOLD WEN1Neg WCLK (4) (1)) (SETUPHOLD REN1Neg RCLK (4) (1)) (SETUP REN1Neg RSNeg (10)) (RECOVERY REN1Neg RSNeg (10)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (6) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (18) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72V821L20TF<SOURCE>IDT data sheet January 1999</SOURCE>IDT72V821L20PF<SOURCE>IDT data sheet January 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING> (DELAY (ABSOLUTE (IOPATH RSNeg EFNeg (4:12:20) (4:12:20)) (IOPATH RCLK EFNeg (2:8:12) (2:8:12)) (IOPATH RCLK PAENeg (2:8:12) (2:8:12)) (IOPATH WCLK FFNeg (2:8:12) (2:8:12)) (IOPATH WCLK PAFNeg (2:8:12) (2:8:12)) (IOPATH RSNeg Q0 (4:12:20) (4:12:20) (4:12:20) (4:12:20) (4:12:20) (4:12:20)) (IOPATH RCLK Q0 (2:8:12) (2:8:12) (2:8:12) (2:8:12) (2:8:12) (2:8:12)) (IOPATH OENeg Q0 (3:7:10) (3:7:10) (3:7:10) (0:7:10) (3:7:10) (0:7:10)) )) (TIMINGCHECK (PERIOD (posedge RCLK) (20)) (PERIOD (posedge WCLK) (20)) (WIDTH (posedge RCLK) (8)) (WIDTH (negedge RCLK) (8)) (WIDTH (negedge RSNeg) (20)) (SETUPHOLD D0 WCLK (5) (1)) (SETUPHOLD WEN1Neg WCLK (5) (1)) (SETUPHOLD REN1Neg RCLK (5) (1)) (SETUP REN1Neg RSNeg (12)) (RECOVERY REN1Neg RSNeg (12)) )) (CELL (CELLTYPE "VITALbuf") (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE ( DEVICE (8) ) ) ) ) (CELL (CELLTYPE "VITALbuf" ) (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE ( DEVICE (20) ) ) )</TIMING></FMFTIME></BODY></FTML>⌨️ 快捷键说明
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