idt72v235.ftm

来自「VHDL的ram和fifo model code 包含众多的厂家」· FTM 代码 · 共 120 行

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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT72V235 Parts</TITLE><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0     R. Munden   99 APR 05   Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT72V235<FMFTIME>IDT72V235L10PF<SOURCE>IDT data sheet January 1999</SOURCE>IDT72V235L10TF<SOURCE>IDT data sheet January 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH RCLK  Q0 (2:4:6.5) (2:4:6.5))     (IOPATH RSNeg EFORNeg (3:10:15) (3:10:15))     (IOPATH RSNeg Q0 (3:10:15) (3:10:15))     (IOPATH OENeg Q0 (1:4:6) (1:4:6) (1:4:6) (1:4:6) (1:4:6) (1:4:6))     (IOPATH WCLK  FFIRNeg (1:4:6.5) (1:4:6.5))     (IOPATH RCLK  EFORNeg (1:4:6.5) (1:4:6.5))     (IOPATH RCLK  PAFNeg (3:9:17) (3:9:17))     (IOPATH WCLK  PAFNeg (2:5:8) (2:5:8))     (IOPATH WCLK  PAENeg (3:9:17) (3:9:17))     (IOPATH RCLK  PAENeg (2:5:8) (2:5:8))     (IOPATH RCLK  WXOHFNeg (3:9:17) (3:9:17))     (IOPATH RCLK  RXONeg (2:5:8) (2:5:8))    ))   (TIMINGCHECK     (PERIOD (posedge RCLK) (10))     (WIDTH (posedge RCLK) (4.5))     (WIDTH (negedge RCLK) (4.5))     (SETUPHOLD D0 (posedge WCLK) (3) (0.5))     (WIDTH (negedge RSNeg) (10))     (SETUP LDNeg (posedge RSNeg) (8) )     (WIDTH (negedge RXINeg) (3))     (SETUP RXINeg (posedge RCLK) (3) )     (SETUPHOLD RENNeg (posedge RCLK) (3) (0.5))   ))    (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE (DEVICE  (5)))))   (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE (DEVICE  (14))))</TIMING></FMFTIME><FMFTIME>IDT72V235L15PF<SOURCE>IDT data sheet January 1999</SOURCE>IDT72V235L15TF<SOURCE>IDT data sheet January 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH RCLK  Q0 (2:6:10) (2:6:10))     (IOPATH RSNeg EFORNeg (3:10:15) (3:10:15))     (IOPATH RSNeg Q0 (3:10:15) (3:10:15))     (IOPATH OENeg Q0 (3:6:8) (3:6:8) (3:6:8) (3:6:8) (3:6:8) (3:6:8))     (IOPATH WCLK  FFIRNeg (2:6:10) (2:6:10))     (IOPATH RCLK  EFORNeg (2:6:10) (2:6:10))     (IOPATH RCLK  PAFNeg (4:12:20) (4:12:20))     (IOPATH WCLK  PAFNeg (2:6:10) (2:6:10))     (IOPATH WCLK  PAENeg (4:12:20) (4:12:20))     (IOPATH RCLK  PAENeg (2:6:10) (2:6:10))     (IOPATH RCLK  WXOHFNeg (4:12:20) (5:12:20))     (IOPATH RCLK  RXONeg (2:6:10) (2:6:10))    ))   (TIMINGCHECK     (PERIOD (posedge RCLK) (15))     (WIDTH (posedge RCLK) (6))     (WIDTH (negedge RCLK) (6))     (SETUPHOLD D0 (posedge WCLK) (4) (1))     (WIDTH (negedge RSNeg) (15))     (SETUP LDNeg (posedge RSNeg) (10) ))     (WIDTH (negedge RXINeg) (6.5))     (SETUP RXINeg (posedge RCLK) (5) )     (SETUPHOLD RENNeg (posedge RCLK) (4) (1))   ))    (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE (DEVICE  (6)))))   (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE (DEVICE  (18))))</TIMING></FMFTIME><FMFTIME>IDT72V235L20TF<SOURCE>IDT data sheet January 1999</SOURCE>IDT72V235L20PF<SOURCE>IDT data sheet January 1999</SOURCE><COMMENT>The Values listed are for VCC=3.0V to 3.6V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH RCLK  Q0 (2:8:12) (2:8:12))     (IOPATH RSNeg EFORNeg (5:15:20) (5:15:20))     (IOPATH RSNeg Q0 (5:15:20) (5:15:20))     (IOPATH OENeg Q0 (3:7:10) (3:7:10) (3:7:10) (3:7:10) (3:7:10) (3:7:10))     (IOPATH WCLK  FFIRNeg (2:8:12) (2:8:12))     (IOPATH RCLK  EFORNeg (2:8:12) (2:8:12))     (IOPATH RCLK  PAFNeg (5:15:22) (5:15:22))     (IOPATH WCLK  PAFNeg (2:8:12) (2:8:12))     (IOPATH WCLK  PAENeg (5:15:22) (5:15:22))     (IOPATH RCLK  PAENeg (2:8:12) (2:8:12))     (IOPATH RCLK  WXOHFNeg (5:15:22) (5:15:22))     (IOPATH RCLK  RXONeg (2:8:12) (2:8:12))    ))   (TIMINGCHECK     (PERIOD (posedge RCLK) (20))     (WIDTH (posedge RCLK) (8))     (WIDTH (negedge RCLK) (8))     (SETUPHOLD D0 (posedge WCLK) (5) (1))     (WIDTH (negedge RSNeg) (20))     (SETUP LDNeg (posedge RSNeg) (12) )     (WIDTH (negedge RXINeg) (8))     (SETUP RXINeg (posedge RCLK) (8) )     (SETUPHOLD RENNeg (posedge RCLK) (5) (1))   ))    (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE (DEVICE  (8)))))   (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE (DEVICE  (20))))</TIMING></FMFTIME></BODY></FTML>

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