idt72142.vhd

VHDL的ram和fifo model code 包含众多的厂家

                    Count := WRPoint + TotalLoc + 1 - RDPoint;
                END IF;
   --             Count := Count + 1;
            ELSE
                wr_inhibit := true;
            END IF;
            IF Count < Ael THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '0';
            ELSIF Count < Half THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '1';
            ELSIF Count < Aeh THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '1';
            ELSIF Count < TotalLOC THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '0';
            ELSE
                AEFNeg_zd := '0';
            END IF;
            IF mode = single THEN
                IF Count < Half THEN
                    XONeg_zd := '1';
                ELSE
                    XONeg_zd := '0';
                END IF;
            ELSE
                IF Count = TotalLOC - 1 THEN
                    XONeg_zd := '0';
                ELSE
                    XONeg_zd := '1';
                END IF;
            END IF;
        ELSE
            IF mode /= single THEN
                XONeg_zd := '1';
            END IF;
        END IF;
    END IF;

    -- parallel out
    IF falling_edge(RNeg_ipd) AND EFNeg_int = '1' AND reset_done THEN 
        IF rd_stat = act THEN
            DataDrive := to_slv(MemData(RDPoint), DataWidth);
            IF RDPoint = TotalLoc THEN
                RDPoint := 0;
            ELSE
                RDPoint := RDPoint + 1;
            END IF;
            IF WRPoint >= RDPoint THEN
                Count := WRPoint - RDPoint;
            ELSE
                Count := WRPoint + TotalLoc + 1 - RDPoint;
            END IF;
   --         Count := Count - 1;
            IF Count = 0 THEN
                EFNeg_zd := '0';
                IF mode /= single THEN
                    XONeg_zd := '0';
                END IF;
            END IF;
        END IF;
    ELSIF rising_edge(RNeg_ipd) AND rd_stat = act THEN
        FFNeg_zd := '1';
        IF Count < Ael THEN
            AEFNeg_zd := '0';
            IF mode = single THEN
                XONeg_zd := '1';
            END IF;
        ELSIF Count < Half THEN
            AEFNeg_zd := '1';
            IF mode = single THEN
                XONeg_zd := '1';
            END IF;
        ELSIF Count < Aeh THEN
            AEFNeg_zd := '1';
            IF mode = single THEN
                XONeg_zd := '0';
            END IF;
        ELSIF Count = TotalLOC THEN
            AEFNeg_zd := '0';
            IF mode = single THEN
                XONeg_zd := '0';
            END IF;
        END IF;
        wr_inhibit := false;
        IF mode /= single AND Count = 0 THEN
            XONeg_zd := '1';
            rd_stat := inact;
        END IF;
    END IF;

    IF falling_edge(FLNeg_ipd) THEN
        IF XINeg_nwv = '0' THEN
            RDPoint := 0;
            Count := WRPoint;
            IF Count = 0 THEN
                EFNeg_zd := '0';
            ELSIF Count < Ael THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '0';
                XONeg_zd := '1';
            ELSIF Count < Half THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '1';
                XONeg_zd := '1';
            ELSIF Count < Aeh THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '1';
                XONeg_zd := '0';
            ELSIF Count < TotalLOC THEN
                FFNeg_zd := '1';
                AEFNeg_zd := '0';
                XONeg_zd := '0';
            ELSE
                FFNeg_zd := '0';
                AEFNeg_zd := '0';
                XONeg_zd := '0';
            END IF;
        END IF;
    ELSIF falling_edge(XINeg_ipd) AND mode = other_exp THEN
        IF wr_stat = inact THEN
            wr_stat := act;
        ELSE
            rd_stat := act;
        END IF;
    END IF;

    IF OENeg_nwv = '0' AND RNeg_nwv = '0' AND rd_stat = act THEN
        Q_zd <= DataDrive;
    ELSE
        Q_zd <= (others => 'Z');
    END IF;


    ----------------------------------------------------------------------------
    -- Path Delay Section
    ----------------------------------------------------------------------------
    VitalPathDelay01 (
        OutSignal       => D8,
        OutSignalName   => "D8",
        OutTemp         => D8_zd,
        GlitchData      => D8_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => RSNeg'LAST_EVENT,
              PathDelay         => tpd_RSNeg_D7,
              PathCondition     => true),
        1 => (InputChangeTime   => SICP'LAST_EVENT,
              PathDelay         => tpd_SICP_D7,
              PathCondition     => true)
        )
    );

    VitalPathDelay01 (
        OutSignal       => D7,
        OutSignalName   => "D7",
        OutTemp         => D7_zd,
        GlitchData      => D7_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => RSNeg'LAST_EVENT,
              PathDelay         => tpd_RSNeg_D7,
              PathCondition     => true),
        1 => (InputChangeTime   => SICP'LAST_EVENT,
              PathDelay         => tpd_SICP_D7,
              PathCondition     => true)
        )
    );

    VitalPathDelay01 (
        OutSignal       => FFNeg_int,
        OutSignalName   => "FFNeg",
        OutTemp         => FFNeg_zd,
        GlitchData      => FF_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => RSNeg'LAST_EVENT,
              PathDelay         => tpd_RSNeg_FFNeg,
              PathCondition     => true),
        1 => (InputChangeTime   => SICP'LAST_EVENT,
              PathDelay         => tpd_SICP_FFNeg,
              PathCondition     => true),
        2 => (InputChangeTime   => RNeg'LAST_EVENT,
              PathDelay         => tpd_RNeg_FFNeg,
              PathCondition     => true)
        )
    );

    VitalPathDelay01 (
        OutSignal       => EFNeg_int,
        OutSignalName   => "EFNeg",
        OutTemp         => EFNeg_zd,
        GlitchData      => EF_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => RSNeg'LAST_EVENT,
              PathDelay         => tpd_RSNeg_EFNeg,
              PathCondition     => true),
        1 => (InputChangeTime   => SICP'LAST_EVENT,
              PathDelay         => tpd_SICP_EFNeg,
              PathCondition     => (mode = single)),
        2 => (InputChangeTime   => RNeg'LAST_EVENT,
              PathDelay         => tpd_SICP_EFNeg,
              PathCondition     => (mode = single)),
        3 => (InputChangeTime   => SICP'LAST_EVENT,
              PathDelay         => tpd_RNeg_EFNeg,
              PathCondition     => (mode /= single)),
        4 => (InputChangeTime   => RNeg'LAST_EVENT,
              PathDelay         => tpd_RNeg_EFNeg,
              PathCondition     => (mode /= single))
        )
    );

    VitalPathDelay01 (
        OutSignal       => XONeg,
        OutSignalName   => "XONeg",
        OutTemp         => XONeg_zd,
        GlitchData      => XO_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => RSNeg'LAST_EVENT,
              PathDelay         => tpd_RSNeg_XONeg,
              PathCondition     => true),
        1 => (InputChangeTime   => SICP'LAST_EVENT,
              PathDelay         => tpd_SICP_XONeg,
              PathCondition     => true),
        2 => (InputChangeTime   => RNeg'LAST_EVENT,
              PathDelay         => tpd_RNeg_XONeg,
              PathCondition     => true)
        )
    );

    VitalPathDelay01 (
        OutSignal       => AEFNeg,
        OutSignalName   => "AEFNeg",
        OutTemp         => AEFNeg_zd,
        GlitchData      => AEF_GlitchData,
        XOn             => XOn,
        MsgOn           => MsgOn,
        Paths           => (
        0 => (InputChangeTime   => RSNeg'LAST_EVENT,
              PathDelay         => tpd_RSNeg_AEFNeg,
              PathCondition     => true),
        1 => (InputChangeTime   => SICP'LAST_EVENT,
              PathDelay         => tpd_SICP_AEFNeg,
              PathCondition     => true),
        2 => (InputChangeTime   => RNeg'LAST_EVENT,
              PathDelay         => tpd_RNeg_AEFNeg,
              PathCondition     => true)
        )
    );


    END PROCESS;

    ----------------------------------------------------------------------------
    -- Path Delay Processes generated as a function of data width
    ----------------------------------------------------------------------------
    DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
        DataOut_Delay : PROCESS (Q_zd(i))
          VARIABLE Q_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
        BEGIN
            VitalPathDelay01Z (
                OutSignal       => QOut(i),
                OutSignalName   => "Q",
                OutTemp         => Q_zd(i),
                Mode            => VitalTransport,
                GlitchData      => Q_GlitchData(i),
                Paths           => (
                    0 => (InputChangeTime => RNeg_ipd'LAST_EVENT,
                          PathDelay       => tpd_RNeg_Q0,
                          PathCondition   => TRUE),
                    1 => (InputChangeTime => OENeg_ipd'LAST_EVENT,
                          PathDelay       => tpd_OENeg_Q0,
                          PathCondition   => TRUE)
               )
           );
        END PROCESS;
    END GENERATE;

END vhdl_behavioral;