idt72v3670.vhd

VHDL的ram和fifo model code 包含众多的厂家

            RefSignal       => PRSNegIn,
            RefSignalName   => "PRSNeg",
            Recovery        => trecovery_RENNeg_MRSNeg,
            ActiveLow       => true,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => RD_RENNeg_PRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Rviol_RENNeg_PRSNeg
        );

        -- tRSR
        VitalRecoveryRemovalCheck (
            TestSignal      => WENNegIn,
            TestSignalName  => "WENNeg",
            RefSignal       => PRSNegIn,
            RefSignalName   => "PRSNeg",
            Recovery        => trecovery_RENNeg_MRSNeg,
            ActiveLow       => true,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & partID,
            TimingData      => RD_WENNeg_PRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Rviol_WENNeg_PRSNeg
        );

        -- tRS
        VitalPeriodPulseCheck (
            TestSignal      => MRSNegIn,
            TestSignalName  => "MRSNeg",
            PulseWidthLow   => tpw_MRSNeg_negedge,
            HeaderMsg       => InstancePath & partID,
            CheckEnabled    => TRUE,
            PeriodData      => PD_MRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_MRSNeg
        );

        -- tRS
        VitalPeriodPulseCheck (
            TestSignal      => PRSNegIn,
            TestSignalName  => "PRSNeg",
            PulseWidthLow   => tpw_MRSNeg_negedge,
            HeaderMsg       => InstancePath & partID,
            CheckEnabled    => TRUE,
            PeriodData      => PD_PRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_PRSNeg
        );

        -- tCLKL, tCLKH
        VitalPeriodPulseCheck (
            TestSignal      => RCLKIn,
            TestSignalName  => "RCLK",
            PulseWidthLow   => tpw_RCLK_negedge,
            PulseWidthHigh  => tpw_RCLK_posedge,
            HeaderMsg       => InstancePath & partID,
            CheckEnabled    => TRUE,
            PeriodData      => PD_RCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_RCLK
        );
        -- tCLKL, tCLKH
        VitalPeriodPulseCheck (
            TestSignal      => WCLKIn,
            TestSignalName  => "WCLK",
            PulseWidthLow   => tpw_RCLK_negedge,
            PulseWidthHigh  => tpw_RCLK_posedge,
            HeaderMsg       => InstancePath & partID,
            CheckEnabled    => TRUE,
            PeriodData      => PD_WCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Pviol_WCLK
        );

        Violation := Tviol_D_WCLK OR Tviol_WENNeg_WCLK OR Tviol_WENNeg_RCLK OR
                     Tviol_SENNeg_WCLK OR Tviol_LDNeg_WCLK OR Tviol_LDNeg_RCLK
                     OR Tviol_WENNeg_MRSNeg OR Tviol_RENNeg_MRSNeg OR
                     Tviol_SENNeg_MRSNeg OR Tviol_FWFT_MRSNeg OR
                     Tviol_FSEL1_MRSNeg OR Tviol_FSEL0_MRSNeg OR
                     Tviol_BM_MRSNeg OR Tviol_OW_MRSNeg OR Tviol_IW_MRSNeg OR
                     Tviol_RM_MRSNeg OR Tviol_IP_MRSNeg OR Tviol_LDNeg_MRSNeg
                     OR Tviol_BENeg_MRSNeg OR Tviol_RTNeg_MRSNeg OR
                     Tviol_RTNeg_PRSNeg OR Tviol_RENNeg_PRSNeg OR
                     Tviol_SENNeg_PRSNeg OR Tviol_WENNeg_PRSNeg OR
                     Tviol_RENNeg_RCLK OR Tviol_RTNeg_RCLK OR
                     Rviol_RENNeg_MRSNeg OR Rviol_WENNeg_MRSNeg OR
                     Rviol_FWFT_MRSNeg OR Rviol_LDNeg_MRSNeg OR
                     Rviol_RENNeg_PRSNeg OR Rviol_WENNeg_PRSNeg OR Pviol_MRSNeg
                     OR Pviol_PRSNeg OR Pviol_RCLK OR Pviol_WCLK;

    END IF;

    ----------------------------------------------------------------------------
    -- Functionality Section
    ----------------------------------------------------------------------------
    IF falling_edge(MRSNegIn) THEN 
        mreset<= false, true AFTER 15 ns; 
        fwftcnt := 0;
        PAENeg_zd := '0';
        PAFNeg_zd := '1';
        HFNeg_zd := '1';
        IF FWFTIn = '1' THEN
            fwft := true;
            EFNeg_zd := '1';
            FFNeg_zd := '0';
            rdptr := 0;
            wrptr := 0;
            count := 0;
        ELSE
            fwft := false;       --idt standard mode
            EFNeg_zd := '0';
            FFNeg_zd := '1';
            rdptr := 1;
            wrptr := 1;
            count := 0; 
        END IF;
        
        delayed_ff:= false;
        delayed_ef:= false;
        FFNeg_dly := FFNeg_zd;
        EFNeg_dly := EFNeg_zd;
        
        IF BENegIn = '0' THEN
            be := true;
        ELSIF BENegIn = '1' THEN
            be := false;
        ELSE
            ASSERT FALSE
            REPORT "BENeg has unusable value"
            SEVERITY error;
        END IF;
        IF BMIn = '0' THEN
            bm := false;
        ELSIF BMIn = '1' THEN
            bm := true;
        ELSE
            ASSERT FALSE
            REPORT "BM has unusable value"
            SEVERITY error;
        END IF;
        IF IWIn = '0' THEN
            iw := false;
        ELSIF IWIn = '1' THEN
            iw := true;
        ELSE
            ASSERT FALSE
            REPORT "IW has unusable value"
            SEVERITY error;
        END IF;
        IF OWIn = '0' THEN
            ow := false;
        ELSIF OWIn = '1' THEN
            ow := true;
        ELSE
            ASSERT FALSE
            REPORT "OW has unusable value"
            SEVERITY error;
        END IF;
        
         --bus matching byte order
        bm_Incnt :=0;
        bm_Outcnt:=0;
        fl_Outcnt:=0;
        
        IF IPIn = '0' THEN
            ip := false;
        ELSIF IPIn = '1' THEN
            ip := true;
        ELSE
            ASSERT FALSE
            REPORT "IP has unusable value"
            SEVERITY error;
        END IF;
        IF PFMIn = '0' THEN
            spfm := false;       -- async programmable flag mode
        ELSIF PFMIn = '1' THEN
            spfm := true;        -- sync programmable flag mode
        ELSE
            ASSERT FALSE
            REPORT "PFM has unusable value"
            SEVERITY error;
        END IF;
        IF RMIn = '0' THEN
            nlrtm := false;
        ELSIF RMIn = '1' THEN
            nlrtm := true;
        ELSE
            ASSERT FALSE
            REPORT "RM has unusable value"
            SEVERITY error;
        END IF;
        IF LDNegIn = '0' THEN
            programming := parallel;
            fp_Incnt := 0;
        ELSE
            programming := serial;
            fs_Incnt := 0;
        END IF;
        opireg := (LDNegIn, FSEL1In, FSEL0In);
        opi := To_Nat(opireg);
        paeoff := offsetps(opi);
        pafoff := TotalLoc - offsetps(opi);
        Qreg := (others => '0');
        mrs_done := true;
    ELSIF falling_edge(PRSNegIn) AND NOT MRSNegIn = '0' THEN
        fwftcnt := 0;
        PAENeg_zd := '0';
        PAFNeg_zd := '1';
        HFNeg_zd := '1';
        IF fwft THEN
            EFNeg_zd := '1';
            FFNeg_zd := '0';
            rdptr := 0;
            wrptr := 0;
            count := 0;
        ELSE
            EFNeg_zd := '0';
            FFNeg_zd := '1';
            rdptr := 1;
            wrptr := 1;
            count := 0;
        END IF;
        
        delayed_ff:= false;
        delayed_ef:= false;
        FFNeg_dly := FFNeg_zd;
        EFNeg_dly := EFNeg_zd;
                
        Qreg := (others => '0');
         --bus matching byte order
        bm_Incnt :=0;
        bm_Outcnt:=0;
        fl_Outcnt:=0;    
    END IF;

-- write side

    IF rising_edge(WCLKIn) AND mreset THEN
        tWCLKposedge := NOW;
        IF (tWCLKposedge - tRCLKposedge) > tSKEW1 THEN
            minskew1RW := true;
        ELSE
            minskew1RW := false;
        END IF;
        IF (tWCLKposedge - tRCLKposedge) > tSKEW2 THEN
            minskew2WR := true;
        ELSE
            minskew2WR := false;
        END IF;
        
        IF LDNegIn = '1' THEN
            -- write to memory
            IF delayed_ff THEN
                FFNeg_zd := FFNeg_dly;
                delayed_ff := false;
            END IF;
            IF WENNegIn = '0' THEN
                IF (FFNeg_zd = '1' AND not fwft) OR
                                           -- NOT full and idt Standard mode
                   (FFNeg_zd = '0' AND fwft) OR 
                   (bm_Incnt>0) THEN       -- input sequence has begun

                    IF bm = false OR iw = false THEN -- port width = 36
                        IF (count>=0 ) THEN          --(count=0 AND NOT fwft)
                            memA(wrptr) := to_nat(DIn(35 downto 27));
                            memB(wrptr) := to_nat(DIn(26 downto 18));
                            memC(wrptr) := to_nat(DIn(17 downto 9));
                            memD(wrptr) := to_nat(DIn(8 downto 0));
                        END IF;
                        IF (count=0 AND fwft) THEN
                                      -- first word fall through in fwft mode
                            outreg := DIn;     --?
                        END IF;
                    ELSIF iw THEN      --bus matching
                        IF NOT ow  THEN -- x18 WRITE , x36 READ
                            IF bm_Incnt=0 THEN
                                IF (count>=0 ) THEN  
                                    memA(wrptr) := to_nat(DIn(17 downto 9));
                                    memB(wrptr) := to_nat(DIn(8 downto 0));
                                ELSIF (count=0 AND fwft) THEN
                                    -- first word fall through in fwft mode
                                    IF be THEN -- Big Endian
                                       outtmp(35 downto 18) := DIn(17 downto 0);
                                    ELSE   
                                        outtmp(17 downto 0) := DIn(17 downto 0);
                                    END IF;    
                                END IF;                               

                            ELSIF bm_Incnt=1 THEN
                                IF (count>=0 ) THEN  
                                    memC(wrptr) := to_nat(DIn(17 downto 9));
                                    memD(wrptr) := to_nat(DIn(8 downto 0));
                                ELSIF (count=0 AND fwft) THEN
                                    -- first word fall through in fwft mode
                                    IF be THEN -- Big Endian
                                        outtmp(17 downto 0) := DIn(17 downto 0);
                                    ELSE   
                                       outtmp(35 downto 18) := DIn(17 downto 0);
                                    END IF;   
                                    outreg:=outtmp;
                                END IF;
                            END IF;    
                        
                        ELSIF  ow   THEN  --x9 WRITE, x36 READ
                            IF bm_Incnt=0 THEN
                                IF (count>=0 ) THEN  
                                    memA(wrptr) := to_nat(DIn(8 downto 0));
                                ELSI