📄 idt72v3670.vhd
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VARIABLE TD_RTNeg_RCLK : VitalTimingDataType; VARIABLE Rviol_RENNeg_MRSNeg : X01 := '0'; VARIABLE RD_RENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_MRSNeg : X01 := '0'; VARIABLE RD_WENNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_FWFT_MRSNeg : X01 := '0'; VARIABLE RD_FWFT_MRSNeg : VitalTimingDataType; VARIABLE Rviol_LDNeg_MRSNeg : X01 := '0'; VARIABLE RD_LDNeg_MRSNeg : VitalTimingDataType; VARIABLE Rviol_RENNeg_PRSNeg : X01 := '0'; VARIABLE RD_RENNeg_PRSNeg : VitalTimingDataType; VARIABLE Rviol_WENNeg_PRSNeg : X01 := '0'; VARIABLE RD_WENNeg_PRSNeg : VitalTimingDataType; VARIABLE Pviol_MRSNeg : X01 := '0'; VARIABLE PD_MRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_PRSNeg : X01 := '0'; VARIABLE PD_PRSNeg : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_RCLK : X01 := '0'; VARIABLE PD_RCLK : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Pviol_WCLK : X01 := '0'; VARIABLE PD_WCLK : VitalPeriodDataType := VitalPeriodDataInit; -- Memory array declaration TYPE MemStore IS ARRAY (0 to TotalLOC + 1) OF NATURAL RANGE 0 TO MaxData; -- Functionality Results Variables VARIABLE Violation : X01 := '0'; VARIABLE EFNeg_zd : std_ulogic; VARIABLE EFNeg_dly : std_ulogic; VARIABLE HFNeg_zd : std_ulogic; VARIABLE FFNeg_zd : std_ulogic; VARIABLE FFNeg_dly : std_ulogic; VARIABLE PAFNeg_zd : std_ulogic; VARIABLE PAENeg_zd : std_ulogic; VARIABLE Qreg : std_logic_vector(35 downto 0) := (others => '0'); VARIABLE mrs_done : boolean := false; VARIABLE fwft : boolean := false; VARIABLE be : boolean := false; VARIABLE bm : boolean := false; VARIABLE iw : boolean := false; VARIABLE ow : boolean := false; VARIABLE ip : boolean := false; VARIABLE spfm : boolean := false; VARIABLE nlrtm : boolean := false; VARIABLE minskew1RW : boolean := true; VARIABLE minskew2WR : boolean := true; VARIABLE delayed_ef : boolean := false; VARIABLE delayed_ff : boolean := false; VARIABLE memA : MemStore; VARIABLE memB : MemStore; VARIABLE memC : MemStore; VARIABLE memD : MemStore; VARIABLE programming : programming_method; VARIABLE tRCLKposedge : Time := 0 ns; VARIABLE tWCLKposedge : Time := 0 ns; VARIABLE rdptr : natural RANGE 0 TO TotalLOC + 1; --read pointer VARIABLE wrptr : natural RANGE 0 TO TotalLOC + 1; --write pointer VARIABLE paeoff : natural RANGE 0 TO TotalLOC; --pae offset VARIABLE pafoff : natural RANGE 0 TO TotalLOC; --paf offset VARIABLE opi : natural RANGE 0 TO 7; --offset preset index VARIABLE count : natural RANGE 0 TO TotalLOC + 1; --memory used VARIABLE fwftcnt : natural RANGE 0 TO 3; -- fwft RCLK counter VARIABLE opireg : std_logic_vector(2 downto 0); VARIABLE outreg : std_logic_vector(35 downto 0); VARIABLE outtmp : std_logic_vector(35 downto 0); VARIABLE bm_reg : std_logic_vector(2 downto 0); VARIABLE bm_Incnt : natural RANGE 0 TO 3 := 0; VARIABLE bm_Outcnt: natural RANGE 0 TO 3 := 0; VARIABLE fl_Outcnt: natural RANGE 0 TO 3 := 0; VARIABLE tmp_reg : std_logic_vector(16 downto 0); VARIABLE fp_Incnt : natural RANGE 0 to 5 := 0; VARIABLE fs_Incnt : natural RANGE 0 to 26 := 0; VARIABLE tmp_ser_in : std_logic_vector(25 downto 0) := (OTHERS=>'0'); VARIABLE zl_retransmit : boolean :=false; VARIABLE sl_retransmit : boolean :=false; -- Output Glitch Detection Variables VARIABLE FFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAFNeg_GlitchData : VitalGlitchDataType; VARIABLE EFNeg_GlitchData : VitalGlitchDataType; VARIABLE PAENeg_GlitchData : VitalGlitchDataType; VARIABLE HFNeg_GlitchData : VitalGlitchDataType; BEGIN ---------------------------------------------------------------------------- -- Timing Check Section ---------------------------------------------------------------------------- IF (TimingChecksOn) THEN -- tDS, tDH VitalSetupHoldCheck ( TestSignal => DIn, TestSignalName => "D", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_D0_WCLK, SetupLow => tsetup_D0_WCLK, HoldHigh => thold_D0_WCLK, HoldLow => thold_D0_WCLK, CheckEnabled => (WENNegIn = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_D_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D_WCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_RCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_WCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_WCLK ); -- tENS, tENH VitalSetupHoldCheck ( TestSignal => RTNegIn, TestSignalName => "RTNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_RENNeg_RCLK, SetupLow => tsetup_RENNeg_RCLK, HoldHigh => thold_RENNeg_RCLK, HoldLow => thold_RENNeg_RCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_RTNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RTNeg_RCLK ); -- tLDS, tLDH VitalSetupHoldCheck ( TestSignal => LDNegIn, TestSignalName => "LDNeg", RefSignal => WCLKIn, RefSignalName => "WCLK", SetupHigh => tsetup_LDNeg_WCLK, SetupLow => tsetup_LDNeg_WCLK, HoldHigh => thold_LDNeg_WCLK, HoldLow => thold_LDNeg_WCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LDNeg_WCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_WCLK ); -- tLDS, tLDH VitalSetupHoldCheck ( TestSignal => LDNegIn, TestSignalName => "LDNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_LDNeg_WCLK, SetupLow => tsetup_LDNeg_WCLK, HoldHigh => thold_LDNeg_WCLK, HoldLow => thold_LDNeg_WCLK, CheckEnabled => true, RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_LDNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_LDNeg_RCLK ); -- tRTS VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => RCLKIn, RefSignalName => "RCLK", SetupHigh => tsetup_WENNeg_RCLK, SetupLow => tsetup_WENNeg_RCLK, CheckEnabled => (RTNegIn = '0'), RefTransition => '/', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_RCLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_RCLK ); -- tRSS VitalSetupHoldCheck ( TestSignal => RENNegIn, TestSignalName => "RENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_RENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RENNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => WENNegIn, TestSignalName => "WENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_WENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WENNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => SENNegIn, TestSignalName => "SENNeg", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true, RefTransition => '\', HeaderMsg => InstancePath & PartID, TimingData => TD_SENNeg_MRSNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SENNeg_MRSNeg ); -- tRSS VitalSetupHoldCheck ( TestSignal => FWFTIn, TestSignalName => "FWFT", RefSignal => MRSNegIn, RefSignalName => "MRSNeg", SetupHigh => tsetup_RENNeg_MRSNeg, SetupLow => tsetup_RENNeg_MRSNeg, CheckEnabled => true,
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