idt72v3670.vhd

VHDL的ram和fifo model code 包含众多的厂家

    SIGNAL RM_ipd              : std_ulogic := 'U';
    SIGNAL RTNeg_ipd           : std_ulogic := 'U';
    SIGNAL OENeg_ipd           : std_ulogic := 'U';
    SIGNAL LDNeg_ipd           : std_ulogic := 'U';
    SIGNAL RENNeg_ipd          : std_ulogic := 'U';
    SIGNAL SENNeg_ipd          : std_ulogic := 'U';
    SIGNAL RCLK_ipd            : std_ulogic := 'U';

    -- SKEW stuff

    ALIAS  tSKEW1          : VitalDelayType IS tdevice_SKEW1;
    ALIAS  tSKEW2          : VitalDelayType IS tdevice_SKEW2;
    SIGNAL OpenIn, OpenOut : std_logic;

BEGIN

--------------------------------------------------------------------------------
-- Dummy instances for exporting tSKEW vals from SDF file
-- using DEVICE construct
--------------------------------------------------------------------------------

  SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1));
  SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_10 : VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_11 : VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_12 : VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_13 : VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_14 : VitalWireDelay (D13_ipd, D13, tipd_D13);
        w_15 : VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_16 : VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_17 : VitalWireDelay (D16_ipd, D16, tipd_D16);
        w_18 : VitalWireDelay (D17_ipd, D17, tipd_D17);
        w_19 : VitalWireDelay (D18_ipd, D18, tipd_D18);
        w_20 : VitalWireDelay (D19_ipd, D19, tipd_D19);
        w_21 : VitalWireDelay (D20_ipd, D20, tipd_D20);
        w_22 : VitalWireDelay (D21_ipd, D21, tipd_D21);
        w_23 : VitalWireDelay (D22_ipd, D22, tipd_D22);
        w_24 : VitalWireDelay (D23_ipd, D23, tipd_D23);
        w_25 : VitalWireDelay (D24_ipd, D24, tipd_D24);
        w_26 : VitalWireDelay (D25_ipd, D25, tipd_D25);
        w_27 : VitalWireDelay (D26_ipd, D26, tipd_D26);
        w_28 : VitalWireDelay (D27_ipd, D27, tipd_D27);
        w_29 : VitalWireDelay (D28_ipd, D28, tipd_D28);
        w_30 : VitalWireDelay (D29_ipd, D29, tipd_D29);
        w_31 : VitalWireDelay (D30_ipd, D30, tipd_D30);
        w_32 : VitalWireDelay (D31_ipd, D31, tipd_D31);
        w_33 : VitalWireDelay (D32_ipd, D32, tipd_D32);
        w_34 : VitalWireDelay (D33_ipd, D33, tipd_D33);
        w_35 : VitalWireDelay (D34_ipd, D34, tipd_D34);
        w_36 : VitalWireDelay (D35_ipd, D35, tipd_D35);
        w_78 : VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        w_79 : VitalWireDelay (BENeg_ipd, BENeg, tipd_BENeg);
        w_80 : VitalWireDelay (MRSNeg_ipd, MRSNeg, tipd_MRSNeg);
        w_81 : VitalWireDelay (PRSNeg_ipd, PRSNeg, tipd_PRSNeg);
        w_82 : VitalWireDelay (FWFT_ipd, FWFT, tipd_FWFT);
        w_83 : VitalWireDelay (OW_ipd, OW, tipd_OW);
        w_84 : VitalWireDelay (FSEL0_ipd, FSEL0, tipd_FSEL0);
        w_85 : VitalWireDelay (FSEL1_ipd, FSEL1, tipd_FSEL1);
        w_86 : VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg);
        w_87 : VitalWireDelay (IW_ipd, IW, tipd_IW);
        w_88 : VitalWireDelay (PFM_ipd, PFM, tipd_PFM);
        w_89 : VitalWireDelay (IP_ipd, IP, tipd_IP);
        w_90 : VitalWireDelay (BM_ipd, BM, tipd_BM);
        w_91 : VitalWireDelay (RM_ipd, RM, tipd_RM);
        w_92 : VitalWireDelay (RTNeg_ipd, RTNeg, tipd_RTNeg);
        w_93 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_94 : VitalWireDelay (LDNeg_ipd, LDNeg, tipd_LDNeg);
        w_95 : VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg);
        w_96 : VitalWireDelay (SENNeg_ipd, SENNeg, tipd_SENNeg);
        w_97 : VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            DIn         : IN    std_logic_vector(35 DOWNTO 0);
            WCLKIn      : IN    std_ulogic := 'U';
            BENegIn     : IN    std_ulogic := 'U';
            MRSNegIn    : IN    std_ulogic := 'U';
            PRSNegIn    : IN    std_ulogic := 'U';
            FWFTIn      : IN    std_ulogic := 'U';
            OWIn        : IN    std_ulogic := 'U';
            FSEL0In     : IN    std_ulogic := 'U';
            FSEL1In     : IN    std_ulogic := 'U';
            WENNegIn    : IN    std_ulogic := 'U';
            IWIn        : IN    std_ulogic := 'U';
            PFMIn       : IN    std_ulogic := 'U';
            IPIn        : IN    std_ulogic := 'U';
            BMIn        : IN    std_ulogic := 'U';
            RMIn        : IN    std_ulogic := 'U';
            RTNegIn     : IN    std_ulogic := 'U';
            OENegIn     : IN    std_ulogic := 'U';
            LDNegIn     : IN    std_ulogic := 'U';
            RENNegIn    : IN    std_ulogic := 'U';
            SENNegIn    : IN    std_ulogic := 'U';
            RCLKIn      : IN    std_ulogic := 'U';
            QOut        : OUT   std_logic_vector(35 downto 0);
            FFNegOut    : OUT   std_ulogic := 'U';
            EFNegOut    : OUT   std_ulogic := 'U';
            HFNegOut    : OUT   std_ulogic := 'U';
            PAFNegOut   : OUT   std_ulogic := 'U';
            PAENegOut   : OUT   std_ulogic := 'U'
         );
        PORT MAP (
            DIn(0) => D0_ipd,
            DIn(1) => D1_ipd,
            DIn(2) => D2_ipd,
            DIn(3) => D3_ipd,
            DIn(4) => D4_ipd,
            DIn(5) => D5_ipd,
            DIn(6) => D6_ipd,
            DIn(7) => D7_ipd,
            DIn(8) => D8_ipd,
            DIn(9) => D9_ipd,
            DIn(10) => D10_ipd,
            DIn(11) => D11_ipd,
            DIn(12) => D12_ipd,
            DIn(13) => D13_ipd,
            DIn(14) => D14_ipd,
            DIn(15) => D15_ipd,
            DIn(16) => D16_ipd,
            DIn(17) => D17_ipd,
            DIn(18) => D18_ipd,
            DIn(19) => D19_ipd,
            DIn(20) => D20_ipd,
            DIn(21) => D21_ipd,
            DIn(22) => D22_ipd,
            DIn(23) => D23_ipd,
            DIn(24) => D24_ipd,
            DIn(25) => D25_ipd,
            DIn(26) => D26_ipd,
            DIn(27) => D27_ipd,
            DIn(28) => D28_ipd,
            DIn(29) => D29_ipd,
            DIn(30) => D30_ipd,
            DIn(31) => D31_ipd,
            DIn(32) => D32_ipd,
            DIn(33) => D33_ipd,
            DIn(34) => D34_ipd,
            DIn(35) => D35_ipd,
            QOut(0) => Q0,
            QOut(1) => Q1,
            QOut(2) => Q2,
            QOut(3) => Q3,
            QOut(4) => Q4,
            QOut(5) => Q5,
            QOut(6) => Q6,
            QOut(7) => Q7,
            QOut(8) => Q8,
            QOut(9) => Q9,
            QOut(10) => Q10,
            QOut(11) => Q11,
            QOut(12) => Q12,
            QOut(13) => Q13,
            QOut(14) => Q14,
            QOut(15) => Q15,
            QOut(16) => Q16,
            QOut(17) => Q17,
            QOut(18) => Q18,
            QOut(19) => Q19,
            QOut(20) => Q20,
            QOut(21) => Q21,
            QOut(22) => Q22,
            QOut(23) => Q23,
            QOut(24) => Q24,
            QOut(25) => Q25,
            QOut(26) => Q26,
            QOut(27) => Q27,
            QOut(28) => Q28,
            QOut(29) => Q29,
            QOut(30) => Q30,
            QOut(31) => Q31,
            QOut(32) => Q32,
            QOut(33) => Q33,
            QOut(34) => Q34,
            QOut(35) => Q35,
            WCLKIn => WCLK_ipd,
            BENegIn => To_UX01(BENeg_ipd),
            MRSNegIn => To_UX01(MRSNeg_ipd),
            PRSNegIn => To_UX01(PRSNeg_ipd),
            FWFTIn => To_UX01(FWFT_ipd),
            OWIn => To_UX01(OW_ipd),
            FSEL0In => To_UX01(FSEL0_ipd),
            FSEL1In => To_UX01(FSEL1_ipd),
            WENNegIn => To_UX01(WENNeg_ipd),
            IWIn => To_UX01(IW_ipd),
            PFMIn => To_UX01(PFM_ipd),
            IPIn => To_UX01(IP_ipd),
            BMIn => To_UX01(BM_ipd),
            RMIn => To_UX01(RM_ipd),
            RTNegIn => To_UX01(RTNeg_ipd),
            OENegIn => To_UX01(OENeg_ipd),
            LDNegIn => To_UX01(LDNeg_ipd),
            RENNegIn => To_UX01(RENNeg_ipd),
            SENNegIn => SENNeg_ipd,
            RCLKIn => RCLK_ipd,
            FFNegOut => FFNeg,
            EFNegOut => EFNeg,
            HFNegOut => HFNeg,
            PAFNegOut => PAFNeg,
            PAENegOut => PAENeg
        );

    SIGNAL Q_zd : std_logic_vector(35 downto 0) := (others => 'Z');
    SIGNAL mreset :  boolean := false;
    
    BEGIN
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Fifo : PROCESS (DIn, WCLKIn, BENegIn, MRSNegIn, PRSNegIn, FWFTIn,
                        OWIn, FSEL0In, FSEL1In, WENNegIn, IWIn, PFMIn, IPIn,
                        BMIn, RMIn, RTNegIn, OENegIn, LDNegIn, RENNegIn,
                        SENNegIn, RCLKIn)

            TYPE programming_method IS (parallel, serial);
            TYPE offset_type IS ARRAY (0 TO 7) OF positive;

            CONSTANT offsetps : offset_type :=
                               (127, 255, 511, 63, 1023, 15, 31, 7);

            -- Timing Check Variables
            VARIABLE Tviol_D_WCLK        : X01 := '0';
            VARIABLE TD_D_WCLK           : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_WCLK   : X01 := '0';
            VARIABLE TD_WENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_RCLK   : X01 := '0';
            VARIABLE TD_WENNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_WCLK   : X01 := '0';
            VARIABLE TD_SENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_WCLK    : X01 := '0';
            VARIABLE TD_LDNeg_WCLK       : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_RCLK    : X01 := '0';
            VARIABLE TD_LDNeg_RCLK       : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_FWFT_MRSNeg   : X01 := '0';
            VARIABLE TD_FWFT_MRSNeg      : VitalTimingDataType;

            VARIABLE Tviol_FSEL1_MRSNeg  : X01 := '0';
            VARIABLE TD_FSEL1_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_FSEL0_MRSNeg  : X01 := '0';
            VARIABLE TD_FSEL0_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_BM_MRSNeg     : X01 := '0';
            VARIABLE TD_BM_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_OW_MRSNeg     : X01 := '0';
            VARIABLE TD_OW_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_IW_MRSNeg     : X01 := '0';
            VARIABLE TD_IW_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_RM_MRSNeg     : X01 := '0';
            VARIABLE TD_RM_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_IP_MRSNeg     : X01 := '0';
            VARIABLE TD_IP_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_MRSNeg  : X01 := '0';
            VARIABLE TD_LDNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_BENeg_MRSNeg  : X01 := '0';
            VARIABLE TD_BENeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_MRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_PRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_PRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_RCLK   : X01 := '0';
            VARIABLE TD_RENNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_RCLK    : X01 := '0';