📄 idt723613.vhd
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TestSignal => SW0, TestSignalName => "SW0", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tSWS, SetupLow => tSWS, HoldHigh => tSWH, HoldLow => tSWH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SW0_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SW0_CLKB); -- SW1/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => SW1, TestSignalName => "SW1", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tSWS, SetupLow => tSWS, HoldHigh => tSWH, HoldLow => tSWH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_SW1_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_SW1_CLKB); -- ODDEVEN/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => ODDEVEN, TestSignalName => "ODDEVEN", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tPGS, SetupLow => tPGS, HoldHigh => tPGH, HoldLow => tPGH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_ODDEVEN_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_ODDEVEN_CLKB); -- PGB/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => PGB, TestSignalName => "PGB", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tPGS, SetupLow => tPGS, HoldHigh => tPGH, HoldLow => tPGH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_PGB_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_PGB_CLKB); -- RSTNeg/CLKA setup/hold time check VitalSetupHoldCheck ( TestSignal => RSTNeg, TestSignalName => "RSTNeg", RefSignal => CLKA, RefSignalName => "CLKA", SetupHigh => tRSTS, SetupLow => tRSTS, HoldHigh => tRSTH, HoldLow => tRSTH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RSTNeg_CLKA, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSTNeg_CLKA); -- RSTNeg/CLKB setup/hold time check VitalSetupHoldCheck ( TestSignal => RSTNeg, TestSignalName => "RSTNeg", RefSignal => CLKB, RefSignalName => "CLKB", SetupHigh => tRSTS, SetupLow => tRSTS, HoldHigh => tRSTH, HoldLow => tRSTH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_RSTNeg_CLKB, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSTNeg_CLKB); -- FS0/RSTNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS0, TestSignalName => "FS0", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS0_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS0_RSTNeg); -- FS1/RSTNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS1, TestSignalName => "FS1", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS1_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS1_RSTNeg); Violation := Pviol_CLKA OR Pviol_CLKB OR Tviol_A0_CLKA OR TViol_B0_CLKB OR Tviol_CSANeg_CLKA OR Tviol_WRA_CLKA OR Tviol_ENA_CLKA OR Tviol_MBA_CLKA OR Tviol_ENB_CLKB OR Tviol_WRB_CLKB OR Tviol_CSBNeg_CLKB OR Tviol_SIZ0_CLKB OR Tviol_SIZ1_CLKB OR Tviol_BENeg_CLKB OR Tviol_SW0_CLKB OR Tviol_SW1_CLKB OR Tviol_ODDEVEN_CLKB OR Tviol_PGB_CLKB OR Tviol_RSTNeg_CLKA OR Tviol_RSTNeg_CLKB OR Tviol_FS0_RSTNeg OR Tviol_FS1_RSTNeg; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorret due timing violation(s)" SEVERITY Warning; END IF; END PROCESS TimingChecks;---------------------------------------------------------------------------------- Functionality Section ---------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- Store Control Input Buses -------------------------------------------------------------------------------- SWint <= (SW1, SW0); MBBint <= '1' when (SIZ0, SIZ1) = SIZMail else '0'; Store_SIZB: PROCESS (CLKB) BEGIN IF CLKB'Event AND CLKB = '1' THEN IF MBBint = '0' THEN SIZBint <= (SIZ1, SIZ0); END IF; END IF; END PROCESS; Store_SIZBprev: PROCESS (CLKB) BEGIN IF CLKB'Event AND CLKB = '1' THEN SIZBprevint <= SIZBint; END IF; END PROCESS; Store_BENeg: PROCESS (CLKB) BEGIN IF CLKB'Event AND CLKB = '1' THEN IF MBBint = '0' THEN BEint <= NOT BENeg; END IF; END IF; END PROCESS; Story_Almost_Flags_Offs: PROCESS (RSTNeg) VARIABLE Offs: Natural RANGE 0 TO FIFOSize-1; VARIABLE FS: std_logic_vector(1 DOWNTO 0); BEGIN IF RSTNeg'Event AND (RSTNeg = '1') AND (RSTNeg'LAST_VALUE = '0') THEN FS := (FS1 & FS0); CASE FS IS WHEN "00" => Offs := 4; WHEN "01" => Offs := 8; WHEN "10" => Offs := 12; WHEN "11" => Offs := 16; WHEN OTHERS => NULL; END CASE; EmptyOffsRegint <= Offs; FullOffsRegint <= FIFOSize - Offs; END IF; END PROCESS; -------------------------------------------------------------------------------- -- Count Clocks during RSTNeg is active or passive -------------------------------------------------------------------------------- Count_CLKA: PROCESS (CLKA, CLKB, CLKB, RSTNeg) BEGIN IF RSTNeg'Event THEN IF (RSTNeg = '0') OR (RSTNeg'LAST_VALUE = '0') THEN IF RSTNeg'LAST_VALUE = '0' THEN IF (CountCLKAint < 4) OR (CountCLKBint < 4) OR (CountCLKBint < 4) THEN ASSERT FALSE REPORT InstancePath & partID & ": During RESET should be 4 posedges on CLKA, CLKB, CLKB"; END IF; END IF; CountCLKAint <= 0; CountCLKBint <= 0; END IF; ELSE IF CLKA'EVENT AND CLKA = '1' THEN IF CountCLKAint < 4 THEN CountCLKAint <= CountCLKAint + 1; END IF; ELSIF CLKB'EVENT AND CLKB = '1' THEN IF CountCLKBint < 4 THEN CountCLKBint <= CountCLKBint + 1; END IF; END IF; END IF; END PROCESS; -------------------------------------------------------------------------------- -- FIFO1 -------------------------------------------------------------------------------- -- Drive Write Enable Signal -------------------------------------------------------------------------------- Drive_EnWrFIFO1: PROCESS(ENA, CSANeg, WRA, MBA) BEGIN IF (ENA = '1') AND (CSANeg = '0') AND (WRA = '1') AND (MBA = '0') THEN EnWrFIFO1int <= '1'; ELSE EnWrFIFO1int <= '0'; END IF; END PROCESS; -------------------------------------------------------------------------------- -- FIFO1 Write Data to Input Register from Port-A -------------------------------------------------------------------------------- InputReg1_Write_Data: PROCESS (CLKA) BEGIN IF CLKA'Event AND CLKA = '1' THEN IF (FFNeg_zd = '1') AND (EnWrFIFO1int = '1') THEN InputReg1int <= A_ipd ; InputReg1Readyint <= '1'; ELSE InputReg1Readyint <= '0'; END IF; END IF; END PROCESS; -------------------------------------------------------------------------------- -- FIFO1 Write Data to FIFO -------------------------------------------------------------------------------- FIFO1_Write_Data: PROCESS (CLKA) VARIABLE Data: FIFOWord; BEGIN IF CLKA'Event AND CLKA = '0' THEN IF RSTNeg = '0' THEN WritePtr1int <= 0; ELSIF InputReg1Readyint = '1' THEN FIFOMemory1int (WritePtr1int) <= InputReg1int; WritePtr1int <= (WritePtr1int + 1) MOD FIFOSize; END IF; END IF; END PROCESS; -------------------------------------------------------------------------------- -- FIFO1 Drive Full Flag FF -------------------------------------------------------------------------------- Drive_FF: PROCESS (CLKA) BEGIN IF CLKA'Event AND CLKA = '1' THEN IF (RSTNeg = '0') THEN IF (CountCLKAint = 1) THEN FFNeg_zd <= '0'; FF1int <= '0'; END IF; ELSIF (CountCLKAint = 1) THEN FFNeg_zd <= '1'; ELSIF (FFNeg_zd = '1') AND (EnWrFIFO1int = '1') THEN IF ((WritePtr1int - ReadPtr1int) MOD FIFOSize) = (FIFOSize - 1) -- After Write FIFO will THEN -- be full FFNeg_zd <= '0'; -- Set Active Full Flag FF1int <= '0'; -- Set Flag Stage 1 END IF; ELSIF (FFNeg_zd = '0') THEN -- Now Full Flag FIFO -- is ac⌨️ 快捷键说明
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