idt72t4098.vhd

VHDL的ram和fifo model code 包含众多的厂家

                    bm := false;
                ELSIF BMIn = '1' THEN
                    bm := true;
                ELSE
                    ASSERT FALSE
                    REPORT "BM has unusable value"
                    SEVERITY Warning;
                END IF;
                IF IWIn = '0' THEN
                    iw := false;
                ELSIF IWIn = '1' THEN
                    iw := true;
                ELSE
                    ASSERT FALSE
                    REPORT "IW has unusable value"
                    SEVERITY Warning;
                END IF;
                IF OWIn = '0' THEN
                    ow := false;
                ELSIF OWIn = '1' THEN
                    ow := true;
                ELSE
                    ASSERT FALSE
                    REPORT "OW has unusable value"
                    SEVERITY Warning;
                END IF;

                --bus matching byte counter
                bm_Incnt :=0;
                bm_Outcnt:=0;

                IF WSDRNegIn = '0' THEN
                    mode_wr := SDR;
                ELSIF WSDRNegIn = '1' THEN
                    mode_wr := DDR;
                ELSE
                    ASSERT FALSE
                    REPORT "WSDRNeg has unusable value"
                    SEVERITY Warning;
                END IF;
                IF RSDRNegIn = '0' THEN
                    mode_rd := SDR;
                ELSIF RSDRNegIn = '1' THEN
                    mode_rd := DDR;
                ELSE
                    ASSERT FALSE
                    REPORT "RSDRNeg has unusable value"
                    SEVERITY Warning;
                END IF;

                IF (mode_wr = DDR OR mode_rd = DDR) AND fwft THEN
                    ASSERT FALSE
                    REPORT "FWFT mode is not acceptable for double data rate!"
                    SEVERITY error;
                END IF;

                opireg := (FSEL1In, FSEL0In);
                opi := To_Nat(opireg);
                paeoff := offsetps(opi);

                -- bus-match and rate mode - select input-output combination
                IF NOT(bm) AND NOT(iw) AND NOT(ow) THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR40;
                    ELSE
                        in_mode := DDR40;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR40;
                    ELSE
                        out_mode := DDR40;
                    END IF;
                ELSIF bm AND NOT(iw) AND NOT(ow) THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR40;
                    ELSE
                        in_mode := DDR40;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR20;
                    ELSE
                        out_mode := DDR20;
                    END IF;
                ELSIF bm AND NOT(iw) AND ow THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR40;
                    ELSE
                        in_mode := DDR40;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR10;
                    ELSE
                        out_mode := DDR10;
                    END IF;
                ELSIF bm AND iw AND NOT(ow) THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR20;
                    ELSE
                        in_mode := DDR20;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR40;
                    ELSE
                        out_mode := DDR40;
                    END IF;
                ELSIF bm AND iw AND ow THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR10;
                    ELSE
                        in_mode := DDR10;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR40;
                    ELSE
                        out_mode := DDR40;
                    END IF;
                END IF;

                IF (in_mode=DDR40) OR
                    (in_mode = DDR20 AND out_mode /= SDR40) OR
                    (in_mode = DDR10 AND out_mode /= SDR40) OR
                    (in_mode = SDR40 AND out_mode = DDR40) OR
                    (in_mode = SDR20 AND out_mode = DDR40) OR
                    (in_mode = SDR10 AND out_mode = DDR40) THEN
                    memory_model := mapped;
                    TotalLoc1 := TotalLoc/2;
                    paeoff := (paeoff - 1)/2;
                ELSE
                    memory_model := normal;
                    TotalLoc1 := TotalLoc;
                END IF;
                pafoff := TotalLoc1 - paeoff;
                outreg := (others => '0');
                Qreg := (others => '0');
            END master_reset;

            PROCEDURE partial_reset
            IS
            BEGIN
                mreset <= false, true AFTER 30 ns; -- valid reset signal
                fwftcnt := 0;
                PAENeg_zd := '0';
                PAFNeg_zd := '1';
                PAENeg_dly := '0';
                PAFNeg_dly := '1';
                rdptr := 0;
                wrptr := 0;
                count := 0;
                last_done := none;
                rt_mode := false;
                IF fwft THEN
                    EFNeg_zd := '1';
                    FFNeg_zd := '0';
                ELSE
                    EFNeg_zd := '0';
                    FFNeg_zd := '1';
                END IF;
                Qreg := (others => '0');
                bm_Incnt :=0;
                bm_Outcnt:=0;
            END partial_reset;

            PROCEDURE count_skew
            IS
            BEGIN
                IF (tWCLKposedge - tRCLKposedge) >= tSKEW1 THEN
                minskew1RW := true;
                ELSE
                minskew1RW := false;
                END IF;

                IF (tWCLKposedge - tRCLKnegedge) >= tSKEW2 THEN
                minskew2RW := true;
                ELSE
                minskew2RW := false;
                END IF;

                IF (tWCLKposedge - tRCLKposedge) >= tSKEW3 THEN
                minskew3RW := true;
                ELSE
                minskew3RW := false;
                END IF;

                IF (tRCLKposedge - tWCLKposedge) >= tSKEW1 THEN
                minskew1WR := true;
                ELSE
                minskew1WR := false;
                END IF;

                IF (tRCLKposedge - tWCLKnegedge) >= tSKEW2 THEN
                minskew2WR := true;
                ELSE
                minskew2WR := false;
                END IF;

                IF (tRCLKposedge - tWCLKposedge) >= tSKEW3 THEN
                minskew3WR := true;
                ELSE
                minskew3WR := false;
                END IF;
            END count_skew;

            PROCEDURE write_input
            IS
            BEGIN
                IF Violation = '0' THEN
                    IF DIn(39 downto 30) /= "ZZZZZZZZZZ" THEN
                        Data4 := to_nat(DIn(39 downto 30));
                    END IF;
                    IF DIn(29 downto 20) /= "ZZZZZZZZZZ" THEN
                        Data3 := to_nat(DIn(29 downto 20));
                    END IF;
                    IF DIn(19 downto 10) /= "ZZZZZZZZZZ" THEN
                        Data2 := to_nat(DIn(19 downto 10));
                    END IF;
                    IF DIn(9 downto 0) /= "ZZZZZZZZZZ" THEN
                        Data1 := to_nat(DIn(9 downto 0));
                    END IF;
                ELSE
                    Data4 := -1;
                    Data3 := -1;
                    Data2 := -1;
                    Data1 := -1;
                END IF;
            END write_input;

            PROCEDURE generate_output(pointer : IN Natural)
            IS
            BEGIN
                IF (RCLKIn = '1') THEN
                    time_flag_for_OE <= '1', '0' AFTER tpd_RCLK_Q0(tr01);
                    FROMRCLK := true;
                    FROMOE := false;
                END IF;
                IF memA(pointer) >= 0 THEN
                    Qreg_tmp(39 downto 30) := to_slv(memA(pointer),10);
                ELSE
                    Qreg_tmp(39 downto 30) := (OTHERS => 'X');
                END IF;
                IF memB(pointer) >= 0 THEN
                    Qreg_tmp(29 downto 20) := to_slv(memB(pointer),10);
                ELSE
                    Qreg_tmp(29 downto 20) := (OTHERS => 'X');
                END IF;
                IF memC(pointer) >= 0 THEN
                    Qreg_tmp(19 downto 10) := to_slv(memC(pointer),10);
                ELSE
                    Qreg_tmp(19 downto 10) := (OTHERS => 'X');
                END IF;
                IF memD(pointer) >= 0 THEN
                    Qreg_tmp(9 downto 0)   := to_slv(memD(pointer),10);
                ELSE
                    Qreg_tmp(9 downto 0) := (OTHERS => 'X');
                END IF;
            END generate_output;

            PROCEDURE write_register
            IS
            BEGIN

            IF rising_edge(SCLKIn) THEN
                IF memory_model = mapped THEN
                    IF fs_Incnt=0 THEN
                        tmp_ser_in := (OTHERS=>'0');
                    END IF;
                    IF fs_Incnt<14 THEN
                        tmp_ser_in(fs_Incnt):= SIIn;
                        fs_Incnt:=fs_Incnt+1;
                        paeoff:= to_nat(tmp_ser_in(13 downto 0));
                    ELSE
                        tmp_ser_in(fs_Incnt):= SIIn;
                        fs_Incnt:=fs_Incnt+1;
                        pafoff:= to_nat(tmp_ser_in(27 downto 14));
                    END IF;
                    IF fs_Incnt>27 THEN
                        fs_Incnt:=0;
                        pafoff:=TotalLoc1-pafoff;
                    END IF;
                ELSIF memory_model = normal THEN
                    IF fs_Incnt=0 THEN
                        tmp_ser_in := (OTHERS=>'0');
                    END IF;
                    IF fs_Incnt<15 THEN
                        tmp_ser_in(fs_Incnt):= SIIn;
                        fs_Incnt:=fs_Incnt+1;
                        paeoff:= to_nat(tmp_ser_in(14 downto 0));
                    ELSE
                        tmp_ser_in(fs_Incnt):= SIIn;
                        fs_Incnt:=fs_Incnt+1;
                        pafoff:= to_nat(tmp_ser_in(29 downto 15));
                    END IF;
                    IF fs_Incnt>29 THEN
                        fs_Incnt:=0;
                        pafoff:=TotalLoc-pafoff;
                    END IF;
                END IF;
            END IF;

            END write_register;

            PROCEDURE read_register
            IS
            BEGIN

            IF rising_edge(SCLKIn) THEN
                IF memory_model = mapped THEN
                    IF fs_Incnt < 28 THEN