📄 idt72t4098.vhd
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---------------------------------------------------------------------------------- File Name: idt72t4098.vhd---------------------------------------------------------------------------------- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com/---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- MODIFICATION HISTORY:---- version: | author: | mod date: | changes made:-- 1.0 D.Vukicevic 05 Dec 12 initial version------------------------------------------------------------------------------------ PART DESCRIPTION:---- Library: FLASH MEMORY-- Technology: CMOS-- Part: IDT72T4098---- Description: 32,768 x 40 High-speed TeraSync DDR/SDR FIFO----------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;---------------------------------------------------------------------------------- ENTITY DECLARATION--------------------------------------------------------------------------------ENTITY idt72t4098 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_D24 : VitalDelayType01 := VitalZeroDelay01; tipd_D25 : VitalDelayType01 := VitalZeroDelay01; tipd_D26 : VitalDelayType01 := VitalZeroDelay01; tipd_D27 : VitalDelayType01 := VitalZeroDelay01; tipd_D28 : VitalDelayType01 := VitalZeroDelay01; tipd_D29 : VitalDelayType01 := VitalZeroDelay01; tipd_D30 : VitalDelayType01 := VitalZeroDelay01; tipd_D31 : VitalDelayType01 := VitalZeroDelay01; tipd_D32 : VitalDelayType01 := VitalZeroDelay01; tipd_D33 : VitalDelayType01 := VitalZeroDelay01; tipd_D34 : VitalDelayType01 := VitalZeroDelay01; tipd_D35 : VitalDelayType01 := VitalZeroDelay01; tipd_D36 : VitalDelayType01 := VitalZeroDelay01; tipd_D37 : VitalDelayType01 := VitalZeroDelay01; tipd_D38 : VitalDelayType01 := VitalZeroDelay01; tipd_D39 : VitalDelayType01 := VitalZeroDelay01; tipd_BM : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_FWFT : VitalDelayType01 := VitalZeroDelay01; tipd_HSTL : VitalDelayType01 := VitalZeroDelay01; tipd_IW : VitalDelayType01 := VitalZeroDelay01; tipd_MARK : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_OW : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RCSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RSDRNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_SENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SRENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SI : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WCSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WSDRNeg : VitalDelayType01 := VitalZeroDelay01; -- tpd delays -- tA, tASO, tRCSLZ, tRCSHZ tpd_RCLK_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ, tOHZ, tOE tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tRSF tpd_MRSNeg_EFNeg : VitalDelayType01 := UnitDelay01; -- tWFF tpd_WCLK_FFNeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_RCLK_EFNeg : VitalDelayType01 := UnitDelay01; -- tPAFS tpd_WCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAES tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tERCLK tpd_RCLK_ERCLK : VitalDelayType01 := UnitDelay01; -- tCLKEN tpd_RCLK_ERENNeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tRS tpw_MRSNeg_negedge : VitalDelayType := UnitDelay; -- tCLKL1 tpw_RCLK_SDR_negedge : VitalDelayType := UnitDelay; -- tCLKH1 tpw_RCLK_SDR_posedge : VitalDelayType := UnitDelay; -- tCLKL2 tpw_RCLK_DDR_negedge : VitalDelayType := UnitDelay; -- tCLKH2 tpw_RCLK_DDR_posedge : VitalDelayType := UnitDelay; -- tSCKL tpw_SCLK_negedge : VitalDelayType := UnitDelay; -- tSCKH tpw_SCLK_posedge : VitalDelayType := UnitDelay; -- minimum clock period - 1/max freq -- tCLK1 tperiod_RCLK_SDR_posedge : VitalDelayType := UnitDelay; -- tCLK2 tperiod_RCLK_DDR_posedge : VitalDelayType := UnitDelay; -- tSCLK tperiod_SCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_D0_WCLK : VitalDelayType := UnitDelay; -- tENS tsetup_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tWCSS tsetup_WCSNeg_WCLK : VitalDelayType := UnitDelay; -- tSDS tsetup_SI_SCLK : VitalDelayType := UnitDelay; -- tSENS tsetup_SENNeg_SCLK : VitalDelayType := UnitDelay; -- tRSS tsetup_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- tHRSS tsetup_HSTL_MRSNeg : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_D0_WCLK : VitalDelayType := UnitDelay; -- tENH thold_RENNeg_RCLK : VitalDelayType := UnitDelay; -- tWCSH thold_WCSNeg_WCLK : VitalDelayType := UnitDelay; -- tSDH thold_SI_SCLK : VitalDelayType := UnitDelay; -- tSENH thold_SENNeg_SCLK : VitalDelayType := UnitDelay; -- trecovery values: release times -- tRSR trecovery_RENNeg_MRSNeg : VitalDelayType := UnitDelay; -- tSKEW1 (skew time /RCLK/WCLK(for EF/FF) tdevice_SKEW1 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time /RCLK/WCLK(for EF/FF - DDR mode)) tdevice_SKEW2 : VitalDelayType := UnitDelay; -- tSKEW2 (skew time /RCLK/WCLK(for PAE/PAF) tdevice_SKEW3 : VitalDelayType := UnitDelay; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'U'; D20 : IN std_ulogic := 'U'; D21 : IN std_ulogic := 'U'; D22 : IN std_ulogic := 'U'; D23 : IN std_ulogic := 'U'; D24 : IN std_ulogic := 'U'; D25 : IN std_ulogic := 'U'; D26 : IN std_ulogic := 'U'; D27 : IN std_ulogic := 'U'; D28 : IN std_ulogic := 'U'; D29 : IN std_ulogic := 'U'; D30 : IN std_ulogic := 'U'; D31 : IN std_ulogic := 'U'; D32 : IN std_ulogic := 'U'; D33 : IN std_ulogic := 'U'; D34 : IN std_ulogic := 'U'; D35 : IN std_ulogic := 'U'; D36 : IN std_ulogic := 'U'; D37 : IN std_ulogic := 'U'; D38 : IN std_ulogic := 'U'; D39 : IN std_ulogic := 'U'; Q0 : OUT std_ulogic := 'U'; Q1 : OUT std_ulogic := 'U'; Q2 : OUT std_ulogic := 'U'; Q3 : OUT std_ulogic := 'U'; Q4 : OUT std_ulogic := 'U'; Q5 : OUT std_ulogic := 'U'; Q6 : OUT std_ulogic := 'U'; Q7 : OUT std_ulogic := 'U'; Q8 : OUT std_ulogic := 'U'; Q9 : OUT std_ulogic := 'U'; Q10 : OUT std_ulogic := 'U'; Q11 : OUT std_ulogic := 'U'; Q12 : OUT std_ulogic := 'U'; Q13 : OUT std_ulogic := 'U'; Q14 : OUT std_ulogic := 'U'; Q15 : OUT std_ulogic := 'U'; Q16 : OUT std_ulogic := 'U'; Q17 : OUT std_ulogic := 'U'; Q18 : OUT std_ulogic := 'U'; Q19 : OUT std_ulogic := 'U'; Q20 : OUT std_ulogic := 'U'; Q21 : OUT std_ulogic := 'U'; Q22 : OUT std_ulogic := 'U'; Q23 : OUT std_ulogic := 'U'; Q24 : OUT std_ulogic := 'U'; Q25 : OUT std_ulogic := 'U'; Q26 : OUT std_ulogic := 'U'; Q27 : OUT std_ulogic := 'U'; Q28 : OUT std_ulogic := 'U'; Q29 : OUT std_ulogic := 'U'; Q30 : OUT std_ulogic := 'U'; Q31 : OUT std_ulogic := 'U'; Q32 : OUT std_ulogic := 'U'; Q33 : OUT std_ulogic := 'U'; Q34 : OUT std_ulogic := 'U'; Q35 : OUT std_ulogic := 'U'; Q36 : OUT std_ulogic := 'U'; Q37 : OUT std_ulogic := 'U'; Q38 : OUT std_ulogic := 'U'; Q39 : OUT std_ulogic := 'U'; BM : IN std_ulogic := 'U'; EFNeg : OUT std_ulogic := 'U'; ERCLK : OUT std_ulogic := 'U'; ERENNeg : OUT std_ulogic := 'U'; FFNeg : OUT std_ulogic := 'U'; FSEL0 : IN std_ulogic := 'U'; FSEL1 : IN std_ulogic := 'U'; FWFT : IN std_ulogic := 'U'; HSTL : IN std_ulogic := 'U'; IW : IN std_ulogic := 'U'; MARK : IN std_ulogic := 'U'; MRSNeg : IN std_ulogic := 'U'; OENeg : IN std_ulogic := 'U'; OW : IN std_ulogic := 'U'; PAENeg : OUT std_ulogic := 'U'; PAFNeg : OUT std_ulogic := 'U'; PRSNeg : IN std_ulogic := 'U'; RCLK : IN std_ulogic := 'U'; RCSNeg : IN std_ulogic := 'U'; RENNeg : IN std_ulogic := 'U'; RSDRNeg : IN std_ulogic := 'U'; RTNeg : IN std_ulogic := 'U'; SCLK : IN std_ulogic := 'U'; SENNeg : IN std_ulogic := 'U'; SRENNeg : IN std_ulogic := 'U'; SI : IN std_ulogic := 'U'; SO : OUT std_ulogic := 'U'; WCLK : IN std_ulogic := 'U'; WCSNeg : IN std_ulogic := 'U'; WENNeg : IN std_ulogic := 'U'; WSDRNeg : IN std_ulogic := 'U' ); ATTRIBUTE VITAL_LEVEL0 of idt72t4098 : ENTITY IS TRUE;END idt72t4098;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION--------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of idt72t4098 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;⌨️ 快捷键说明
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