idt72v831.vhd

VHDL的ram和fifo model code 包含众多的厂家

      w_15: VitalWireDelay (RCLK_ipd     , RCLK     , tipd_RCLK      );
      w_16: VitalWireDelay (REN1Neg_ipd  , REN1Neg  , tipd_REN1Neg   );
      w_17: VitalWireDelay (REN2Neg_ipd  , REN2Neg  , tipd_REN2Neg   );
      w_18: VitalWireDelay (OENeg_ipd    , OENeg    , tipd_OENeg     );

    END BLOCK WireDelay;

    -------------------------------------------------------------------
    --  Main behavior Block
    -------------------------------------------------------------------

    VitalBehavior: BLOCK

      PORT (
          D        : IN  std_logic_vector( FIFOWordLenght-1 DOWNTO 0):=
                                          (OTHERS => 'X' );
          RSNeg    : IN  std_logic := 'X';
          WCLK     : IN  std_logic := 'X';
          WEN1Neg  : IN  std_logic := 'X';
          WEN2LDNeg: IN  std_logic := 'X';
          RCLK     : IN  std_logic := 'X';
          REN1Neg  : IN  std_logic := 'X';
          REN2Neg  : IN  std_logic := 'X';
          OENeg    : IN  std_logic := 'X';
          Q        : OUT std_logic_vector( FIFOWordLenght-1 DOWNTO 0):=
                                          (OTHERS => 'U' );
          EFNeg    : OUT std_logic := 'U';
          PAENeg   : OUT std_logic := 'U';
          PAFNeg   : OUT std_logic := 'U';
          FFNeg    : OUT std_logic := 'U');

      PORT MAP (
              D(0)      => D0_ipd,
              D(1)      => D1_ipd,
              D(2)      => D2_ipd,
              D(3)      => D3_ipd,
              D(4)      => D4_ipd,
              D(5)      => D5_ipd,
              D(6)      => D6_ipd,
              D(7)      => D7_ipd,
              D(8)      => D8_ipd,
              RSNeg     => RSNeg_ipd,
              WCLK      => WCLK_ipd,
              WEN1Neg   => WEN1Neg_ipd,
              WEN2LDNeg => WEN2LDNeg_ipd,
              RCLK      => RCLK_ipd,
              REN1Neg   => REN1Neg_ipd,
              REN2Neg   => REN2Neg_ipd,
              OENeg     => OENeg_ipd,
              Q(0)      => Q0,
              Q(1)      => Q1,
              Q(2)      => Q2,
              Q(3)      => Q3,
              Q(4)      => Q4,
              Q(5)      => Q5,
              Q(6)      => Q6,
              Q(7)      => Q7,
              Q(8)      => Q8,
              EFNeg     => EFNeg,
              PAENeg    => PAENeg,
              PAFNeg    => PAFNeg,
              FFNeg     => FFNeg);

    SIGNAL FFNeg_zd      : std_ulogic := 'X';      --------------------
    SIGNAL EFNeg_zd      : std_ulogic := 'X';      -- regs for output
    SIGNAL PAENeg_zd     : std_ulogic := 'X';      -- flags
    SIGNAL PAFNeg_zd     : std_ulogic := 'X';      --------------------
    SIGNAL Q_zd          : std_logic_vector(FIFOWordLenght-1 DOWNTO 0);

      BEGIN  -- VitalBehavior block

        ---------------------------------------------------------------
        -- Timinf Check Section
        ---------------------------------------------------------------
        TimingChecks: PROCESS (D, RSNeg, WCLK, WEN1Neg, WEN2LDNeg,
                               RCLK, REN1Neg, REN2Neg, OENeg )
          -- Timing Check Variable

          -- Pulse Width and Period Check Variables

          VARIABLE Pviol_WCLK      : X01 := '0';
          VARIABLE PD_WCLK         : VitalPeriodDataType :=
                                     VitalPeriodDataInit;

          VARIABLE Pviol_RCLK      : X01 := '0';
          VARIABLE PD_RCLK         : VitalPeriodDataType :=
                                     VitalPeriodDataInit;

          VARIABLE Pviol_RSNeg     : X01 := '0';
          VARIABLE PD_RSNeg        : VitalPeriodDataType :=
                                     VitalPeriodDataInit;

          -- Setup/Hold Check Variables

          VARIABLE Tviol_D0_WCLK       : X01 := '0';
          VARIABLE TD_D0_WCLK          : VitalTimingDataType;

          VARIABLE Tviol_REN1Neg_RCLK       : X01 := '0';
          VARIABLE TD_REN1Neg_RCLK          : VitalTimingDataType;

          VARIABLE Tviol_REN2Neg_RCLK  : X01 := '0';
          VARIABLE TD_REN2Neg_RCLK     : VitalTimingDataType;

          VARIABLE Tviol_WEN1Neg_WCLK       : X01 := '0';
          VARIABLE TD_WEN1Neg_WCLK          : VitalTimingDataType;

          VARIABLE Tviol_WEN2LDNeg_WCLK  : X01 := '0';
          VARIABLE TD_WEN2LDNeg_WCLK     : VitalTimingDataType;

          VARIABLE Tviol_REN1Neg_RSNeg : X01 := '0';
          VARIABLE TD_REN1Neg_RSNeg    : VitalTimingDataType;

          VARIABLE Tviol_REN2Neg_RSNeg : X01 := '0';
          VARIABLE TD_REN2Neg_RSNeg    : VitalTimingDataType;

          VARIABLE Tviol_WEN1Neg_RSNeg : X01 := '0';
          VARIABLE TD_WEN1Neg_RSNeg    : VitalTimingDataType;

          VARIABLE Tviol_WEN2LDNeg_RSNeg : X01 := '0';
          VARIABLE TD_WEN2LDNeg_RSNeg    : VitalTimingDataType;

          -- Recovery Check Variables

          VARIABLE Rviol_REN1Neg_RSNeg     : X01 := '0';
          VARIABLE RD_REN1Neg_RSNeg        : VitalTimingDataType;

          VARIABLE Rviol_REN2Neg_RSNeg     : X01 := '0';
          VARIABLE RD_REN2Neg_RSNeg        : VitalTimingDataType;

          VARIABLE Rviol_WEN1Neg_RSNeg     : X01 := '0';
          VARIABLE RD_WEN1Neg_RSNeg        : VitalTimingDataType;

          VARIABLE Rviol_WEN2LDNeg_RSNeg     : X01 := '0';
          VARIABLE RD_WEN2LDNeg_RSNeg        : VitalTimingDataType;

          -- Violation variable (used to OR all individual violatiions)

          VARIABLE Violation               : X01 := '0';

        BEGIN  -- timing check process

          IF (TimingChecksON) THEN

            Pviol_WCLK            := '0';
            Pviol_RCLK            := '0';
            Pviol_RSNeg           := '0';
            Tviol_D0_WCLK         := '0';
            Tviol_REN1Neg_RCLK    := '0';
            Tviol_REN2Neg_RCLK    := '0';
            Tviol_WEN1Neg_WCLK    := '0';
            Tviol_WEN2LDNeg_WCLK  := '0';
            Tviol_REN1Neg_RSNeg   := '0';
            Tviol_REN2Neg_RSNeg   := '0';
            Tviol_WEN1Neg_RSNeg   := '0';
            Tviol_WEN2LDNeg_RSNeg := '0';
            Rviol_REN1Neg_RSNeg   := '0';
            Rviol_REN2Neg_RSNeg   := '0';
            Rviol_WEN1Neg_RSNeg   := '0';
            Rviol_WEN2LDNeg_RSNeg := '0';

            --1. WCLK pulse ( low&high ) width and period check
            -- ( tCLK, tCLKL, tCLKH )
            IF WCLK'Event THEN
            VitalPeriodPulseCheck (
              TestSignal      => WCLK,
              TestSignalName  => "WCLK",
              Period          => tperiod_WCLK_posedge,
              PulseWidthHigh  => tpw_RCLK_posedge,
              PulseWidthLow   => tpw_RCLK_negedge,
              CheckEnabled    => TRUE,
              HeaderMsg       => InstancePath & partID,
              PeriodData      => PD_WCLK,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Pviol_WCLK);
            END IF;

            --2. RCLK pulse ( low&high ) width and period check
            -- ( tCLK, tCLKL, tCLKH )
            IF RCLK'Event THEN
            VitalPeriodPulseCheck (
              TestSignal      => RCLK,
              TestSignalName  => "RCLK",
              Period          => tperiod_RCLK_posedge,
              PulseWidthHigh  => tpw_RCLK_posedge,
              PulseWidthLow   => tpw_RCLK_negedge,
              CheckEnabled    => TRUE,
              HeaderMsg       => InstancePath & partID,
              PeriodData      => PD_RCLK,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Pviol_RCLK);
            END IF;

            --3. RSNeg pulse low width check (tRS)
            IF RSNeg'Event THEN
            VitalPeriodPulseCheck (
              TestSignal      => RSNeg,
              TestSignalName  => "RSNeg",
              PulseWidthLow   => tpw_RSNeg_negedge,
              CheckEnabled    => TRUE,
              HeaderMsg       => InstancePath & partID,
              PeriodData      => PD_RSNeg,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Pviol_RSNeg);
            END IF;

            --4. D/WCLK setup/hold time check (tDS, tDH)
            IF D'Event AND WCLK'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => D,
              TestSignalName  => "D",
              RefSignal       => WCLK,
              RefSignalName   => "WCLK",
              SetupHigh       => tSetup_D0_WCLK,
              SetupLow        => tSetup_D0_WCLK,
              HoldHigh        => tHold_D0_WCLK,
              HoldLow         => tHold_D0_WCLK,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_D0_WCLK,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_D0_WCLK);
            END IF;

            --5. WEN1Neg/WCLK setup/hold time check (tENS, tENH)
            IF WEN1Neg'Event AND WCLK'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => WEN1Neg,
              TestSignalName  => "WEN1Neg",
              RefSignal       => WCLK,
              RefSignalName   => "WCLK",
              SetupLow        => tSetup_REN1Neg_RCLK,
              HoldLow         => tHold_REN1Neg_RCLK,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_WEN1Neg_WCLK,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_WEN1Neg_WCLK);
            END IF;

            --6. WEN2LDNeg/WCLK setup/hold time check (tENS, tENH)
            IF WEN2LDNeg'Event AND WCLK'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => WEN2LDNeg,
              TestSignalName  => "WEN2LDNeg",
              RefSignal       => WCLK,
              RefSignalName   => "WCLK",
              SetupHigh       => tSetup_REN1Neg_RCLK,
              SetupLow        => tSetup_REN1Neg_RCLK,
              HoldHigh        => tHold_REN1Neg_RCLK,
              HoldLow         => tHold_REN1Neg_RCLK,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
                      TimingData      => TD_WEN2LDNeg_WCLK,
              XOn             => XOn,
              MsgOn           => MsgOn,
              Violation       => Tviol_WEN2LDNeg_WCLK);
            END IF;

            --7. REN1Neg/RCLK setup/hold time check (tENS, tENH)
            IF REN1Neg'Event AND RCLK'Event THEN
            VitalSetupHoldCheck (
              TestSignal      => REN1Neg,
              TestSignalName  => "REN1Neg",
              RefSignal       => RCLK,
              RefSignalName   => "RCLK",
              SetupLow        => tSetup_REN1Neg_RCLK,
              HoldLow         => tHold_REN1Neg_RCLK,
              CheckEnabled    => TRUE,
              RefTransition    => '/',
              HeaderMsg       => InstancePath & partID,
              TimingData      => TD_REN1Neg_RCLK,
              XOn             => XOn,
              MsgOn           => MsgOn,