📄 idt723612.vhd
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XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RSTNeg_CLKB); -- FS0/RSTNegNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS0, TestSignalName => "FS0", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS0_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS0_RSTNeg); -- FS1/RSTNegNeg setup/hold time check VitalSetupHoldCheck ( TestSignal => FS1, TestSignalName => "FS1", RefSignal => RSTNeg, RefSignalName => "RSTNeg", SetupHigh => tFSS, SetupLow => tFSS, HoldHigh => tFSH, HoldLow => tFSH, CheckEnabled => True, RefTransition => '/', HeaderMsg => InstancePath & partID, TimingData => TD_FS1_RSTNeg, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_FS1_RSTNeg); Violation := Pviol_CLKA OR Pviol_CLKB OR Tviol_A0_CLKA OR TViol_B0_CLKB OR Tviol_CSANeg_CLKA OR Tviol_WRA_CLKA OR Tviol_ENA_CLKA OR Tviol_MBA_CLKA OR Tviol_ENB_CLKB OR Tviol_WRB_CLKB OR Tviol_CSBNeg_CLKB OR Tviol_MBB_CLKB OR Tviol_ODDEVEN_CLKA OR Tviol_PGA_CLKA OR Tviol_ODDEVEN_CLKB OR Tviol_PGB_CLKB OR Tviol_RSTNeg_CLKA OR Tviol_RSTNeg_CLKB OR Tviol_FS0_RSTNeg OR Tviol_FS1_RSTNeg; ASSERT Violation = '0' REPORT InstancePath & partID & " : signal values may be" & " incorret due timing violation(s)" SEVERITY Warning; END IF; END PROCESS TimingChecks;---------------------------------------------------------------------------------- Functionality Section ---------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- Store Control Input Buses-------------------------------------------------------------------------------- Story_Almost_Flags_Offs: PROCESS (RSTNeg) VARIABLE Offs: Natural RANGE 0 TO FIFOSize-1; VARIABLE FS: std_logic_vector(1 DOWNTO 0); BEGIN IF RSTNeg'Event AND (RSTNeg = '1') AND (RSTNeg'LAST_VALUE = '0') THEN FS := (FS1 & FS0); CASE FS IS WHEN "00" => Offs := 4; WHEN "01" => Offs := 8; WHEN "10" => Offs := 12; WHEN "11" => Offs := 16; WHEN OTHERS => NULL; END CASE; EmptyOffsRegint <= Offs; FullOffsRegint <= FIFOSize - Offs; END IF; END PROCESS; ---------------------------------------------------------------------------------- Count Clocks during RSTNeg is active or passive-------------------------------------------------------------------------------- Count_CLKA: PROCESS (CLKA, CLKB, CLKB, RSTNeg) BEGIN IF RSTNeg'Event THEN IF (RSTNeg = '0') OR (RSTNeg'LAST_VALUE = '0') THEN IF RSTNeg'LAST_VALUE = '0' THEN IF (CountCLKAint < 4) OR (CountCLKBint < 4) OR (CountCLKBint < 4) THEN ASSERT FALSE REPORT InstancePath & partID & ": During RESET should be 4 posedges on CLKA, CLKB, CLKB"; END IF; END IF; CountCLKAint <= 0; CountCLKBint <= 0; END IF; ELSE IF CLKA'EVENT AND CLKA = '1' THEN IF CountCLKAint < 4 THEN CountCLKAint <= CountCLKAint + 1; END IF; ELSIF CLKB'EVENT AND CLKB = '1' THEN IF CountCLKBint < 4 THEN CountCLKBint <= CountCLKBint + 1; END IF; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 ---------------------------------------------------------------------------------- Drive Write Enable Signal-------------------------------------------------------------------------------- Drive_EnWrFIFO1: PROCESS(ENA, CSANeg, WRA, MBA) BEGIN IF (ENA = '1') AND (CSANeg = '0') AND (WRA = '1') AND (MBA = '0') THEN EnWrFIFO1int <= '1'; ELSE EnWrFIFO1int <= '0'; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 Write Data to Input Register from Port-A-------------------------------------------------------------------------------- InputReg1_Write_Data: PROCESS (CLKA) BEGIN IF CLKA'Event AND CLKA = '1' THEN IF (FFANeg_zd = '1') AND (EnWrFIFO1int = '1') THEN InputReg1int <= A_ipd ; InputReg1Readyint <= '1'; ELSE InputReg1Readyint <= '0'; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 Write Data to FIFO-------------------------------------------------------------------------------- FIFO1_Write_Data: PROCESS (CLKA) VARIABLE Data: FIFOWord; BEGIN IF CLKA'Event AND CLKA = '0' THEN IF RSTNeg = '0' THEN WritePtr1int <= 0; ELSIF InputReg1Readyint = '1' THEN FIFOMemory1int (WritePtr1int) <= InputReg1int; WritePtr1int <= (WritePtr1int + 1) MOD FIFOSize; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 Drive Full Flag FFA-------------------------------------------------------------------------------- Drive_FFA: PROCESS (CLKA) BEGIN IF CLKA'Event AND CLKA = '1' THEN IF (RSTNeg = '0') THEN IF (CountCLKAint = 1) THEN FFANeg_zd <= '0'; FFA1int <= '0'; END IF; ELSIF (CountCLKAint = 1) THEN FFANeg_zd <= '1'; ELSIF (FFANeg_zd = '1') AND (EnWrFIFO1int = '1') THEN IF ((WritePtr1int - ReadPtr1int) MOD FIFOSize) = (FIFOSize - 1) -- After Write FIFO will THEN -- be full FFANeg_zd <= '0'; -- Set Active Full Flag FFA1int <= '0'; -- Set Flag Stage 1 END IF; ELSIF (FFANeg_zd = '0') THEN -- Now Full Flag FIFO -- is active IF (WritePtr1int /= ReadPtr1int) AND -- In fact FIFO isn't full ((NOW - CLKB'LAST_EVENT) > tdevice_SKEW1) THEN FFA1int <= '1'; -- Reset Flag - Stage 1 END IF; IF FFA1int = '1' THEN -- If Flag Stage 1 already -- has been reset FFANeg_zd <= '1'; -- Reset Full Flag -- (FIFO isn't full) END IF; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 Drive Almost Full Flag AFA-------------------------------------------------------------------------------- Drive_AFA: PROCESS (CLKA) BEGIN IF CLKA'Event AND CLKA = '1' THEN IF (RSTNeg = '0') THEN IF (CountCLKAint = 1) THEN AFANeg_zd <= '1'; END IF; ELSIF (AFANeg_zd = '1') AND (EnWrFIFO1int = '1') THEN IF ((WritePtr1int - ReadPtr1int) MOD FIFOSize) = (FullOffsRegInt - 1) -- After Write FIFO will THEN -- be full at Offs AFANeg_zd <= '0'; -- Set Active Full Flag AFA1int <= '0'; -- Set Flag Stage 1 END IF; ELSIF (AFANeg_zd = '0') THEN -- Now Full Flag FIFO -- is active IF (((WritePtr1int - ReadPtr1int - 1) MOD FIFOSize) < (FullOffsRegint - 1)) AND -- In fact FIFO isn't full ((NOW - CLKB'LAST_EVENT) > tdevice_SKEW2) THEN -- at Offs AFA1int <= '1'; -- Reset Flag - Stage 1 END IF; IF AFA1int = '1' THEN -- If Flag Stage 1 already -- has been reset AFANeg_zd <= '1'; -- Reset Full Flag -- (FIFO isn't full at Offs) END IF; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------------- Drive Read Enable Signal-------------------------------------------------------------------------------- Drive_EnRdFIFO1: PROCESS(ENB, CSBNeg, WRB, MBB) BEGIN IF (ENB = '1') AND (CSBNeg = '0') AND (WRB = '0') AND (MBB = '0') THEN EnRdFIFO1int <= '1'; ELSE EnRdFIFO1int <= '0'; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 Read Data to Output Register -------------------------------------------------------------------------------- FIFO1_Read_Data: PROCESS (CLKB) VARIABLE Data: FIFOWord; BEGIN IF CLKB'Event AND CLKB = '1' THEN IF RSTNeg = '0' THEN ReadPtr1int <= 0; ELSIF (EFBNeg_zd = '1') AND (EnRdFIFO1int = '1') THEN Data := FIFOMemory1int (ReadPtr1int); IF PGB = '1' THEN -- Generate Parity Data := GenParity (Data, ODDEVEN, OutputReg1int'LENGTH); END IF; OutputReg1int <= Data; ReadPtr1int <= (ReadPtr1int + 1) MOD FIFOSize; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 Drive Empty Flag EFB-------------------------------------------------------------------------------- Drive_EFB: PROCESS (CLKB) BEGIN IF CLKB'Event AND CLKB = '1' THEN IF (RSTNeg = '0') THEN IF (CountCLKBint = 1) THEN EFBNeg_zd <= '0'; EFB1int <= '0'; END IF; ELSIF (EFBNeg_zd = '1') and (EnRdFIFO1int = '1') THEN IF ((WritePtr1int - ReadPtr1int) MOD FIFOSize) = 1 THEN -- After Read FIFO will -- be empty EFBNeg_zd <= '0'; -- Set Active Empty Flag EFB1int <= '0'; -- Set Flag Stage 1 END IF; ELSIF (EFBNeg_zd = '0') THEN -- Now Empty Flag FIFO -- is active IF (WritePtr1int /= ReadPtr1int) AND -- In fact FIFO isn't empty ((NOW - CLKA'LAST_EVENT) > tdevice_SKEW1) THEN EFB1int <= '1'; -- Reset Flag - Stage 1 END IF; IF EFB1int = '1' THEN -- If Flag Stage 1 already -- has been reset EFBNeg_zd <= '1'; -- Reset Empty Flag -- (FIFO isn't empty) END IF; END IF; END IF; END PROCESS; ---------------------------------------------------------------------------------- FIFO1 Drive Almost Empty Flag AEB-------------------------------------------------------------------------------- Drive_AEB: PROCESS (CLKB) BEGIN IF CLKB'Event AND CLKB = '1' THEN IF (RSTNeg = '0') THEN IF (CountCLKBint = 1) THEN AEBNeg_zd <= '0'; END IF; ELSIF (AEBNeg_zd = '1') and (EnRdFIFO1int = '1') THEN IF (((WritePtr1int - ReadPtr1int) MOD FIFOSize) = 1 + EmptyOffsRegint) THEN -- After Read FIFO will -- be empty at Offs ⌨️ 快捷键说明
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