idt723614.vhd

VHDL的ram和fifo model code 包含众多的厂家

     
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-- Timing Check Section                                                         --
--------------------------------------------------------------------------------

     TimingChecks: PROCESS ( A_ipd, B_ipd, BENeg, CLKA, CLKB, CSANeg, CSBNeg,
       ENA, ENB, MBA, FS0, FS1, ODDEVEN, PGA, PGB, RSTNeg, SIZ0, SIZ1, SW0, SW1,
       WRA, WRB)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;

    -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_B0_CLKB       : X01 := '0';
      VARIABLE TD_B0_CLKB          : VitalTimingDataType;

      VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENA_CLKA      : X01 := '0';
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_MBA_CLKA      : X01 := '0';
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_CSBNeg_CLKB   : X01 := '0';
      VARIABLE TD_CSBNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_ENB_CLKB      : X01 := '0';
      VARIABLE TD_ENB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_WRB_CLKB      : X01 := '0';
      VARIABLE TD_WRB_CLKB         : VitalTimingDataType;
    
      VARIABLE Tviol_SIZ0_CLKB     : X01 := '0';
      VARIABLE TD_SIZ0_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_SIZ1_CLKB     : X01 := '0';
      VARIABLE TD_SIZ1_CLKB        : VitalTimingDataType;

      VARIABLE Tviol_BENeg_CLKB    : X01 := '0';
      VARIABLE TD_BENeg_CLKB       : VitalTimingDataType;

      VARIABLE Tviol_SW0_CLKB      : X01 := '0';
      VARIABLE TD_SW0_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_SW1_CLKB      : X01 := '0';
      VARIABLE TD_SW1_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_ODDEVEN_CLKA  : X01 := '0';
      VARIABLE TD_ODDEVEN_CLKA     : VitalTimingDataType;

      VARIABLE Tviol_PGA_CLKA      : X01 := '0';
      VARIABLE TD_PGA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ODDEVEN_CLKB  : X01 := '0';
      VARIABLE TD_ODDEVEN_CLKB     : VitalTimingDataType;

      VARIABLE Tviol_PGB_CLKB      : X01 := '0';
      VARIABLE TD_PGB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_RSTNeg_CLKA   : X01 := '0';
      VARIABLE TD_RSTNeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_RSTNeg_CLKB   : X01 := '0';
      VARIABLE TD_RSTNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_FS0_RSTNeg    : X01 := '0';
      VARIABLE TD_FS0_RSTNeg       : VitalTimingDataType;

      VARIABLE Tviol_FS1_RSTNeg    : X01 := '0';
      VARIABLE TD_FS1_RSTNeg       : VitalTimingDataType;

    -- Violation variable (used to OR all individual violation variables)

      VARIABLE Violation           : X01 := '0';
    
BEGIN

--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------
 IF  (TimingChecksOn)
 THEN

      -- CLKA period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKA,
          TestSignalName  => "CLKA",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKA);

      -- CLKB period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKB,
          TestSignalName  => "CLKB",
          Period	  => tCLK,
          PulseWidthHigh  => tCLKH,
          PulseWidthLow   => tCLKL,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKB);

      -- A/CLKA setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => A_ipd,
          TestSignalName  => "A",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSANeg = '0') AND (WRA = '1') 
                              AND (ENA = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_A0_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_A0_CLKA);

   -- C/CLKB setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => B_ipd,
          TestSignalName  => "B",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tDS,
          SetupLow        => tDS,
          HoldHigh        => tDH,
          HoldLow         => tDH,
          CheckEnabled    => (CSANeg = '0') AND (WRA = '1') 
                              AND (ENA = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_B0_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => TViol_B0_CLKB);


      -- CSANeg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSANeg,
          TestSignalName  => "CSANeg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupLow        => tENS,
          SetupHigh       => tENS,
          HoldLow         => tENH,
          HoldHigh        => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSANeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSANeg_CLKA);

      -- WRA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRA,
          TestSignalName  => "WRA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRA_CLKA);

      -- ENA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENA,
          TestSignalName  => "ENA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENA_CLKA);

       -- MBA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBA,
          TestSignalName  => "MBA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBA_CLKA);

      -- ENB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENB,
          TestSignalName  => "ENB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENB_CLKB);

      -- WRB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRB,
          TestSignalName  => "WRB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRB_CLKB);

      -- CSBNeg/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSBNeg,
          TestSignalName  => "CSBNeg",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupLow        => tENS,
          SetupHigh       => tENS,
          HoldLow         => tENH,
          HoldHigh        => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSBNeg_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSBNeg_CLKB);

      -- SIZ0/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => SIZ0,
          TestSignalName  => "SIZ0",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tSZS,
          SetupLow        => tSZS,
          HoldHigh        => tSZH,
          HoldLow         => tSZH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_SIZ0_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_SIZ0_CLKB);

      -- SIZ1/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => SIZ1,
          TestSignalName  => "SIZ1",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tSZS,
          SetupLow        => tSZS,
          HoldHigh        => tSZH,
          HoldLow         => tSZH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_SIZ1_CLKB,
          XOn             => XOn,