idt723614.vhd

VHDL的ram和fifo model code 包含众多的厂家

    A_ipd(12)   => A12_ipd,
    A_ipd(13)   => A13_ipd,
    A_ipd(14)   => A14_ipd,
    A_ipd(15)   => A15_ipd,
    A_ipd(16)   => A16_ipd,
    A_ipd(17)   => A17_ipd,
    A_ipd(18)   => A18_ipd,
    A_ipd(19)   => A19_ipd,
    A_ipd(20)   => A20_ipd,
    A_ipd(21)   => A21_ipd,
    A_ipd(22)   => A22_ipd,
    A_ipd(23)   => A23_ipd,
    A_ipd(24)   => A24_ipd,
    A_ipd(25)   => A25_ipd,
    A_ipd(26)   => A26_ipd,
    A_ipd(27)   => A27_ipd,
    A_ipd(28)   => A28_ipd,
    A_ipd(29)   => A29_ipd,
    A_ipd(30)   => A30_ipd,
    A_ipd(31)   => A31_ipd,
    A_ipd(32)   => A32_ipd,
    A_ipd(33)   => A33_ipd,
    A_ipd(34)   => A34_ipd,
    A_ipd(35)   => A35_ipd,
    A(0)    	=> A0,
    A(1)    	=> A1,
    A(2)    	=> A2,
    A(3)    	=> A3,
    A(4) 	=> A4,
    A(5)  	=> A5,
    A(6)  	=> A6,
    A(7)    	=> A7,
    A(8)    	=> A8,
    A(9)    	=> A9,
    A(10)   	=> A10,
    A(11)   	=> A11,
    A(12)   	=> A12,
    A(13)   	=> A13,
    A(14)   	=> A14,
    A(15)   	=> A15,
    A(16)   	=> A16,
    A(17)   	=> A17,
    A(18)   	=> A18,
    A(19)   	=> A19,
    A(20)   	=> A20,
    A(21)   	=> A21,
    A(22)   	=> A22,
    A(23)   	=> A23,
    A(24)   	=> A24,
    A(25)   	=> A25,
    A(26)   	=> A26,
    A(27)   	=> A27,
    A(28)   	=> A28,
    A(29)   	=> A29,
    A(30)   	=> A30,
    A(31)   	=> A31,
    A(32)   	=> A32,
    A(33)   	=> A33,
    A(34)   	=> A34,
    A(35)    	=> A35,
    AEANeg  	=> AEANeg,
    AEBNeg   	=> AEBNeg,
    AFANeg   	=> AFANeg,
    AFBNeg   	=> AFBNeg,
    B_ipd(0)    => B0_ipd,
    B_ipd(1)    => B1_ipd,
    B_ipd(2)    => B2_ipd,
    B_ipd(3)    => B3_ipd,
    B_ipd(4)    => B4_ipd,
    B_ipd(5)    => B5_ipd,
    B_ipd(6)    => B6_ipd,
    B_ipd(7)    => B7_ipd,
    B_ipd(8)    => B8_ipd,
    B_ipd(9)    => B9_ipd,
    B_ipd(10)   => B10_ipd,
    B_ipd(11)   => B11_ipd,
    B_ipd(12)   => B12_ipd,
    B_ipd(13)   => B13_ipd,
    B_ipd(14)   => B14_ipd,
    B_ipd(15)   => B15_ipd,
    B_ipd(16)   => B16_ipd,
    B_ipd(17)   => B17_ipd,
    B_ipd(18)   => B18_ipd,
    B_ipd(19)   => B19_ipd,
    B_ipd(20)   => B20_ipd,
    B_ipd(21)   => B21_ipd,
    B_ipd(22)   => B22_ipd,
    B_ipd(23)   => B23_ipd,
    B_ipd(24)   => B24_ipd,
    B_ipd(25)   => B25_ipd,
    B_ipd(26)   => B26_ipd,
    B_ipd(27)   => B27_ipd,
    B_ipd(28)   => B28_ipd,
    B_ipd(29)   => B29_ipd,
    B_ipd(30)   => B30_ipd,
    B_ipd(31)   => B31_ipd,
    B_ipd(32)   => B32_ipd,
    B_ipd(33)   => B33_ipd,
    B_ipd(34)   => B34_ipd,
    B_ipd(35)   => B35_ipd,
    B(0)    	=> B0,
    B(1)    	=> B1,
    B(2)    	=> B2,
    B(3)    	=> B3,
    B(4) 	=> B4,
    B(5)  	=> B5,
    B(6)  	=> B6,
    B(7)    	=> B7,
    B(8)    	=> B8,
    B(9)    	=> B9,
    B(10)   	=> B10,
    B(11)   	=> B11,
    B(12)   	=> B12,
    B(13)   	=> B13,
    B(14)   	=> B14,
    B(15)   	=> B15,
    B(16)   	=> B16,
    B(17)   	=> B17,
    B(18)   	=> B18,
    B(19)   	=> B19,
    B(20)   	=> B20,
    B(21)   	=> B21,
    B(22)   	=> B22,
    B(23)   	=> B23,
    B(24)   	=> B24,
    B(25)   	=> B25,
    B(26)   	=> B26,
    B(27)   	=> B27,
    B(28)   	=> B28,
    B(29)   	=> B29,
    B(30)   	=> B30,
    B(31)   	=> B31,
    B(32)   	=> B32,
    B(33)   	=> B33,
    B(34)   	=> B34,
    B(35)    	=> B35,
    BENeg   	=> BENeg_ipd,
    CLKA        => CLKA_ipd,
    CLKB        => CLKB_ipd,
    CSANeg      => CSANeg_ipd,
    CSBNeg      => CSBNeg_ipd,
    EFANeg   	=> EFANeg,
    EFBNeg   	=> EFBNeg,
    ENA         => ENA_ipd,
    ENB         => ENB_ipd,
    FFANeg   	=> FFANeg,
    FFBNeg   	=> FFBNeg,
    FS0         => FS0_ipd,
    FS1         => FS1_ipd,
    MBA         => MBA_ipd,
    MBF1Neg     => MBF1Neg,
    MBF2Neg     => MBF2Neg,
    ODDEVEN     => ODDEVEN_ipd,
    PEFANeg  	=> PEFANeg,
    PEFBNeg  	=> PEFBNeg,
    PGA         => PGA_ipd,
    PGB         => PGB_ipd,
    RSTNeg      => RSTNeg_ipd,
    SIZ0        => SIZ0_ipd,
    SIZ1        => SIZ1_ipd,
    SW0         => SW0_ipd,
    SW1         => SW1_ipd,
    WRA         => WRA_ipd,
    WRB         => WRB_ipd);
    
  -- zero delayed outputs and bidirectional ports 
  -- (func. sec. uses these signals instead of =
  --  actual outputs and bidirectional ports);
  -- actual outputs are assigned in Path Delay Section
  
  SIGNAL A_zd         : std_logic_vector (35 downto 0);
  SIGNAL B_zd         : std_logic_vector (35 downto 0); 
  SIGNAL AEANeg_zd    : std_logic; 
  SIGNAL AEBNeg_zd    : std_logic;  
  SIGNAL AFANeg_zd    : std_logic;  
  SIGNAL AFBNeg_zd    : std_logic;  
  SIGNAL EFANeg_zd    : std_logic;     
  SIGNAL EFBNeg_zd    : std_logic;     
  SIGNAL FFANeg_zd    : std_logic;     
  SIGNAL FFBNeg_zd    : std_logic;     
  SIGNAL MBF1Neg_zd   : std_logic;    
  SIGNAL MBF2Neg_zd   : std_logic;   
  SIGNAL PEFANeg_zd   : std_logic;    
  SIGNAL PEFBNeg_zd   : std_logic;   

  ------------------------------------------------------------------------------
  -- FIFO memory definitions
  ------------------------------------------------------------------------------
  -- general
  CONSTANT FIFOSize        :  positive := 64;
  CONSTANT FIFOWordLength  :  positive := 36;
  SUBTYPE  FIFOWord    IS std_logic_vector(FIFOWordLength - 1 DOWNTO 0);
  TYPE     FIFOArray   IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord;
  
  CONSTANT MailWordLength  :  positive := 36;
  SUBTYPE  MailWord    IS std_logic_vector(MailWordLength - 1 DOWNTO 0);
  
  -- special
  CONSTANT FIFOWordBytes   :  positive := 4;
  
  ------------------------------------------------------------------------------
  -- internal constants 
  ------------------------------------------------------------------------------
  
     CONSTANT SIZByte : std_logic_vector (1 DOWNTO 0) := "10";	
     CONSTANT SIZWord : std_logic_vector (1 DOWNTO 0) := "01";
     CONSTANT SIZLong : std_logic_vector (1 DOWNTO 0) := "00";    
     CONSTANT SIZMail : std_logic_vector (1 DOWNTO 0) := "11";    
  
  ------------------------------------------------------------------------------
  -- internal signals 
  ------------------------------------------------------------------------------  
  
  -- FIFO Arrays
  
     SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
     SIGNAL FIFOMemory2int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
                                        
  -- Main Registers                                       
  
     -- Input Registers
      
     SIGNAL InputReg1int   : FIFOWord := (OTHERS => 'X');
     SIGNAL InputReg2int   : FIFOWord := (OTHERS => 'X'); 
     
     -- Output Registers
      
     SIGNAL OutputReg1int  : FIFOWord := (OTHERS => 'X');
     SIGNAL OutputReg2int  : FIFOWord := (OTHERS => 'X');
     
     -- FIFO Pointers
     
     SIGNAL ReadPtr1int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL ReadPtr2int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr1int   : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr2int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- FIFO Offset for Almoust Empty/Full Flags
     
     SIGNAL EmptyOffsRegint: Natural RANGE 0 TO FIFOSize-1;
     SIGNAL FullOffsRegint : Natural RANGE 0 TO FIFOSize-1;
     
     -- Mail Registers
     
     SIGNAL Mail1int,
            Mail2int       : MailWord := (OTHERS => 'X');
            
     -- Flags Flip-flop first stage (each flag is synchonized 
     -- to its Port Clock through two flip-flop stages)
     
     SIGNAL EFA1int, EFB1int, FFA1int, FFC1int, 
            AEA1int, AEB1int, AFA1int, AFC1int : std_logic;
            
    -- Flags "Input Register is loaded" - in this 
     -- model they will be loaded to FIFOMemory on CLK negedge      
      
     SIGNAL InputReg1Readyint   : std_logic; 
     SIGNAL InputReg2Readyint   : std_logic; 
     SIGNAL InputReg2ReadyNextint   : std_logic; 
     
     -- Pointers for Byte/Word Access for PortB/PortC
        
     SIGNAL OutputReg1Ptrint : Natural RANGE 0 TO FIFOWordBytes-1;
     SIGNAL InputReg2Ptrint  : Natural RANGE 0 TO FIFOWordBytes-1;
     
     SIGNAL OutputReg1Readyint : std_logic; -- all 4-bytes have been
     				 	    -- read to Port-B 
     SIGNAL OutputReg1ReadyNextint : std_logic;
                                            -- all 4-bytes will be 
     				 	    -- read to Port-B next CLKB
     				 	    -- posedge
	     						   
       -- Pointers for Byte/Word Access that will be latched on CLKB posedge
       	     						   
       SIGNAL OutputReg1PtrNextint   : Natural RANGE 0 TO FIFOWordBytes - 1;
       
     -- Registers for control ports 
  
     SIGNAL SWint      : std_logic_vector (1 downto 0);  -- (SW1, SW0) 		
     SIGNAL SIZBint    : std_logic_vector (1 downto 0);  -- (SIZ1, SIZ0) 
                                                          -- on CLKB posedge 	
     SIGNAL BEint      : std_logic;  -- BENeg on CLKB posedge 	
  
     SIGNAL SIZBprevint : std_logic_vector (1 downto 0);  -- (SIZ1, SIZ0) 
 	-- on previous CLKB posedge
 	
     SIGNAL MBBint     : std_logic; -- SIZ0,1 = (1,1) 	
  
     -- Counters of Clocks during RSTNeg is active or passive
     
     SIGNAL CountCLKAint, CountCLKBint: Natural;
  
     -- Internal Control Signals
     
     SIGNAL EnWrFIFO1int, EnRdFIFO1int, EnWrFIFO2int, EnRdFIFO2int,
     	    EnWrMail1int, EnRdMail1int, EnWrMail2int, EnRdMail2int: std_ulogic; 
     	    
    -------------------------------------------------------------------    
    -- Swap Bytes/Words in 36-bit word
    -------------------------------------------------------------------    
    FUNCTION FIFOSwap
      	(Data      : in std_logic_vector (35 downto 0);	-- Data
         SwapCode  : in std_logic_vector (1 downto 0))
       -- SwapCode = "00" - NO SWAP 	
       -- SwapCode = "01" - BYTE SWAP 	
       -- SwapCode = "10" - WORD SWAP 	
       -- SwapCode = "11" - BYTE-WORD SWAP	
         RETURN  std_logic_vector --(35 downto 0)
    IS  
        VARIABLE Result: std_logic_vector (35 downto 0);
    BEGIN
	CASE SwapCode IS
	    WHEN "00" => 
	      Result := Data;
	    WHEN "01" =>
	      Result(8 DOWNTO 0)  := Data(35 DOWNTO 27);
	      Result(17 DOWNTO 9) := Data(26 DOWNTO 18);
	      Result(26 DOWNTO 18):= Data(17 DOWNTO 9);
	      Result(35 DOWNTO 27):= Data(8 DOWNTO 0);
	    WHEN "10" =>
	      Result(17 DOWNTO 0) := Data(35 DOWNTO 18);
	      Result(35 DOWNTO 18):= Data(17 DOWNTO 0);
	    WHEN "11" =>
	      Result(8 DOWNTO 0)  := Data(17 DOWNTO 9);
	      Result(17 DOWNTO 9) := Data(8 DOWNTO 0);
	      Result(26 DOWNTO 18):= Data(35 DOWNTO 27);
	      Result(35 DOWNTO 27):= Data(26 DOWNTO 18);
	    WHEN OTHERS => 
	      Result := (OTHERS => 'X');  
	END CASE;             
    	RETURN Result;
    END FIFOSwap;
    
  BEGIN -- VitalBehavior block