📄 idt723614.vhd

📁 VHDL的ram和fifo model code 包含众多的厂家
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    FFANeg   : OUT   std_logic := 'U'; -- Port-A Full Flag    FFBNeg   : OUT   std_logic := 'U'; -- Port-A Full Flag    FS0      : IN    std_logic := 'X'; -- Flag Offset Select    FS1      : IN    std_logic := 'X'; -- Flag Offset Select    MBA      : IN    std_logic := 'X'; -- Port-A Mailbox Select    MBF1Neg  : OUT   std_logic := 'U'; -- Mail1 Register Flag    MBF2Neg  : OUT   std_logic := 'U'; -- Mail2 Register Flag    ODDEVEN  : IN    std_logic := 'X'; -- Odd/Even parity select    PEFANeg  : OUT   std_logic := 'U'; -- Port-A Parity Error Flag    PEFBNeg  : OUT   std_logic := 'U'; -- Port-B Parity Error Flag    PGA      : IN    std_logic := 'X'; -- Port-A Parity Generation    PGB      : IN    std_logic := 'X'; -- Port-B Parity Generation    RSTNeg   : IN    std_logic := 'X'; -- Reset    SIZ0     : IN    std_logic := 'X'; -- Bus Size Select (Ports B and C)    SIZ1     : IN    std_logic := 'X'; -- Bus Size Select (Ports B and C)    SW0      : IN    std_logic := 'X'; -- Port B Byte Swap    SW1      : IN    std_logic := 'X'; -- Port B Byte Swap    WRA      : IN    std_logic := 'X'; -- Port-A Write/Read Select    WRB      : IN    std_logic := 'X'  -- Port-B Write Enable     );  ATTRIBUTE vital_level0 OF IDT723614 : ENTITY IS True;    END IDT723614;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION                                                   ----------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral OF IDT723614 IS  ATTRIBUTE vital_level1 OF vhdl_behavioral : ARCHITECTURE IS False;  CONSTANT partID : String := "IDT723614";    -- delayed inputs and bidirectional ports    -- (func. sec. must use these signals instead of actual inputs/inoutputs)  SIGNAL A0_ipd       : std_ulogic := 'X';  SIGNAL A1_ipd       : std_ulogic := 'X';  SIGNAL A2_ipd       : std_ulogic := 'X';  SIGNAL A3_ipd       : std_ulogic := 'X';  SIGNAL A4_ipd       : std_ulogic := 'X';  SIGNAL A5_ipd       : std_ulogic := 'X';  SIGNAL A6_ipd       : std_ulogic := 'X';  SIGNAL A7_ipd       : std_ulogic := 'X';  SIGNAL A8_ipd       : std_ulogic := 'X';  SIGNAL A9_ipd       : std_ulogic := 'X';  SIGNAL A10_ipd      : std_ulogic := 'X';  SIGNAL A11_ipd      : std_ulogic := 'X';  SIGNAL A12_ipd      : std_ulogic := 'X';  SIGNAL A13_ipd      : std_ulogic := 'X';  SIGNAL A14_ipd      : std_ulogic := 'X';  SIGNAL A15_ipd      : std_ulogic := 'X';  SIGNAL A16_ipd      : std_ulogic := 'X';  SIGNAL A17_ipd      : std_ulogic := 'X';  SIGNAL A18_ipd      : std_ulogic := 'X';  SIGNAL A19_ipd      : std_ulogic := 'X';  SIGNAL A20_ipd      : std_ulogic := 'X';  SIGNAL A21_ipd      : std_ulogic := 'X';  SIGNAL A22_ipd      : std_ulogic := 'X';  SIGNAL A23_ipd      : std_ulogic := 'X';  SIGNAL A24_ipd      : std_ulogic := 'X';  SIGNAL A25_ipd      : std_ulogic := 'X';  SIGNAL A26_ipd      : std_ulogic := 'X';  SIGNAL A27_ipd      : std_ulogic := 'X';  SIGNAL A28_ipd      : std_ulogic := 'X';  SIGNAL A29_ipd      : std_ulogic := 'X';  SIGNAL A30_ipd      : std_ulogic := 'X';  SIGNAL A31_ipd      : std_ulogic := 'X';  SIGNAL A32_ipd      : std_ulogic := 'X';  SIGNAL A33_ipd      : std_ulogic := 'X';  SIGNAL A34_ipd      : std_ulogic := 'X';  SIGNAL A35_ipd      : std_ulogic := 'X';  SIGNAL B0_ipd       : std_ulogic := 'X';  SIGNAL B1_ipd       : std_ulogic := 'X';  SIGNAL B2_ipd       : std_ulogic := 'X';  SIGNAL B3_ipd       : std_ulogic := 'X';  SIGNAL B4_ipd       : std_ulogic := 'X';  SIGNAL B5_ipd       : std_ulogic := 'X';  SIGNAL B6_ipd       : std_ulogic := 'X';  SIGNAL B7_ipd       : std_ulogic := 'X';  SIGNAL B8_ipd       : std_ulogic := 'X';  SIGNAL B9_ipd       : std_ulogic := 'X';  SIGNAL B10_ipd      : std_ulogic := 'X';  SIGNAL B11_ipd      : std_ulogic := 'X';  SIGNAL B12_ipd      : std_ulogic := 'X';  SIGNAL B13_ipd      : std_ulogic := 'X';  SIGNAL B14_ipd      : std_ulogic := 'X';  SIGNAL B15_ipd      : std_ulogic := 'X';  SIGNAL B16_ipd      : std_ulogic := 'X';  SIGNAL B17_ipd      : std_ulogic := 'X';  SIGNAL B18_ipd      : std_ulogic := 'X';  SIGNAL B19_ipd      : std_ulogic := 'X';  SIGNAL B20_ipd      : std_ulogic := 'X';  SIGNAL B21_ipd      : std_ulogic := 'X';  SIGNAL B22_ipd      : std_ulogic := 'X';  SIGNAL B23_ipd      : std_ulogic := 'X';  SIGNAL B24_ipd      : std_ulogic := 'X';  SIGNAL B25_ipd      : std_ulogic := 'X';  SIGNAL B26_ipd      : std_ulogic := 'X';  SIGNAL B27_ipd      : std_ulogic := 'X';  SIGNAL B28_ipd      : std_ulogic := 'X';  SIGNAL B29_ipd      : std_ulogic := 'X';  SIGNAL B30_ipd      : std_ulogic := 'X';  SIGNAL B31_ipd      : std_ulogic := 'X';  SIGNAL B32_ipd      : std_ulogic := 'X';  SIGNAL B33_ipd      : std_ulogic := 'X';  SIGNAL B34_ipd      : std_ulogic := 'X';  SIGNAL B35_ipd      : std_ulogic := 'X';  SIGNAL BENeg_ipd    : std_ulogic := 'X';  SIGNAL CLKA_ipd     : std_ulogic := 'X';  SIGNAL CLKB_ipd     : std_ulogic := 'X';  SIGNAL CSANeg_ipd   : std_ulogic := 'X';  SIGNAL CSBNeg_ipd   : std_ulogic := 'X';  SIGNAL ENA_ipd      : std_ulogic := 'X';  SIGNAL ENB_ipd      : std_ulogic := 'X';  SIGNAL FS0_ipd      : std_ulogic := 'X';  SIGNAL FS1_ipd      : std_ulogic := 'X';  SIGNAL MBA_ipd      : std_ulogic := 'X';  SIGNAL ODDEVEN_ipd  : std_ulogic := 'X';  SIGNAL PGA_ipd      : std_ulogic := 'X';  SIGNAL PGB_ipd      : std_ulogic := 'X';  SIGNAL RSTNeg_ipd   : std_ulogic := 'X';  SIGNAL SIZ0_ipd     : std_ulogic := 'X';  SIGNAL SIZ1_ipd     : std_ulogic := 'X';  SIGNAL SW0_ipd      : std_ulogic := 'X';  SIGNAL SW1_ipd      : std_ulogic := 'X';  SIGNAL WRA_ipd      : std_ulogic := 'X';  SIGNAL WRB_ipd      : std_ulogic := 'X';      SIGNAL OpenIn, OpenOut : std_logic; -- Additional signals    ALIAS   tA	: VitalDelayType01 	IS tpd_CLKA_A0;  ALIAS   tWFF	: VitalDelayType01	IS tpd_CLKA_FFANeg;  ALIAS   tREF	: VitalDelayType01	IS tpd_CLKA_EFANeg;  ALIAS   tPAE	: VitalDelayType01	IS tpd_CLKA_AEANeg;  ALIAS   tPAF	: VitalDelayType01	IS tpd_CLKA_AFANeg;  ALIAS   tPMF  : VitalDelayType01	IS tpd_CLKA_MBF1Neg;   ALIAS   tPMR  : VitalDelayType01	IS tpd_CLKA_B0;  ALIAS   tPPE	: VitalDelayType01	IS tpd_CLKB_PEFBNeg;  ALIAS   tMDV  : VitalDelayType01	IS tpd_MBA_A0;    ALIAS   tPDPE	: VitalDelayType01	IS tpd_A0_PEFANEg;  ALIAS   tPOPE	: VitalDelayType01	IS tpd_ODDEVEN_PEFANeg;  ALIAS   tPOPB	: VitalDelayType01	IS tpd_ODDEVEN_A8;  ALIAS   tPEPE	: VitalDelayType01	IS tpd_CSANeg_PEFANeg;  ALIAS   tPEPB	: VitalDelayType01	IS tpd_CSANeg_A8;  ALIAS   tRSF  : VitalDelayType01	IS tpd_RSTNeg_MBF1Neg;   ALIAS   tEN_DIS: VitalDelayType01Z	IS tpd_CSANeg_A0;  ALIAS   tCLK	: VitalDelayType	IS tperiod_CLKA_posedge;  ALIAS   tCLKH	: VitalDelayType	IS tpw_CLKA_posedge;  ALIAS   tCLKL	: VitalDelayType	IS tpw_CLKA_negedge;  ALIAS   tDS	: VitalDelayType	IS tsetup_A0_CLKA;  ALIAS   tENS	: VitalDelayType	IS tsetup_CSANeg_CLKA;  ALIAS   tSZS	: VitalDelayType	IS tsetup_SIZ0_CLKB;  ALIAS   tSWS	: VitalDelayType	IS tsetup_SW0_CLKB;  ALIAS   tPGS	: VitalDelayType	IS tsetup_ODDEVEN_CLKA;  ALIAS   tRSTS	: VitalDelayType	IS tsetup_RSTNeg_CLKA;  ALIAS   tFSS	: VitalDelayType	IS tsetup_FS0_RSTNeg;  ALIAS   tDH	: VitalDelayType	IS thold_A0_CLKA;  ALIAS   tENH	: VitalDelayType	IS thold_CSANeg_CLKA;  ALIAS   tSZH	: VitalDelayType	IS thold_SIZ0_CLKB;  ALIAS   tSWH 	: VitalDelayType	IS thold_SW0_CLKB;  ALIAS   tPGH	: VitalDelayType	IS thold_ODDEVEN_CLKA;  ALIAS   tRSTH	: VitalDelayType	IS thold_RSTNeg_CLKA;  ALIAS   tFSH	: VitalDelayType	IS thold_FS0_RSTNeg;BEGIN---------------------------------------------------------------------------------- Skew Delays ---------------------------------------------------------------------------------- Artificient VITAL primitives wich allows pass complex non-constaint -- SKEW time into the model            SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1));SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));---------------------------------------------------------------------------------- Wire Delays                                                                ----------------------------------------------------------------------------------WireDelay : BLOCKBEGIN    w_1:  VitalWireDelay (A0_ipd,       A0,       tipd_A0      );    w_2:  VitalWireDelay (A1_ipd,       A1,       tipd_A1      );    w_3:  VitalWireDelay (A2_ipd,       A2,       tipd_A2      );    w_4:  VitalWireDelay (A3_ipd,       A3,       tipd_A3      );    w_5:  VitalWireDelay (A4_ipd,       A4,       tipd_A4      );    w_6:  VitalWireDelay (A5_ipd,       A5,       tipd_A5      );    w_7:  VitalWireDelay (A6_ipd,       A6,       tipd_A6      );    w_8:  VitalWireDelay (A7_ipd,       A7,       tipd_A7      );    w_9:  VitalWireDelay (A8_ipd,       A8,       tipd_A8      );    w_10: VitalWireDelay (A9_ipd,       A9,       tipd_A9      );    w_11: VitalWireDelay (A10_ipd,      A10,      tipd_A10     );    w_12: VitalWireDelay (A11_ipd,      A11,      tipd_A11     );    w_13: VitalWireDelay (A12_ipd,      A12,      tipd_A12     );    w_14: VitalWireDelay (A13_ipd,      A13,      tipd_A13     );    w_15: VitalWireDelay (A14_ipd,      A14,      tipd_A14     );    w_16: VitalWireDelay (A15_ipd,      A15,      tipd_A15     );    w_17: VitalWireDelay (A16_ipd,      A16,      tipd_A16     );    w_18: VitalWireDelay (A17_ipd,      A17,      tipd_A17     );    w_19: VitalWireDelay (A18_ipd,      A18,      tipd_A18     );    w_20: VitalWireDelay (A19_ipd,      A19,      tipd_A19     );    w_21: VitalWireDelay (A20_ipd,      A20,      tipd_A20     );    w_22: VitalWireDelay (A21_ipd,      A21,      tipd_A21     );    w_23: VitalWireDelay (A22_ipd,      A22,      tipd_A22     );    w_24: VitalWireDelay (A23_ipd,      A23,      tipd_A23     );    w_25: VitalWireDelay (A24_ipd,      A24,      tipd_A24     );    w_26: VitalWireDelay (A25_ipd,      A25,      tipd_A25     );    w_27: VitalWireDelay (A26_ipd,      A26,      tipd_A26     );    w_28: VitalWireDelay (A27_ipd,      A27,      tipd_A27     );    w_29: VitalWireDelay (A28_ipd,      A28,      tipd_A28     );    w_30: VitalWireDelay (A29_ipd,      A29,      tipd_A29     );    w_31: VitalWireDelay (A30_ipd,      A30,      tipd_A30     );    w_32: VitalWireDelay (A31_ipd,      A31,      tipd_A31     );    w_33: VitalWireDelay (A32_ipd,      A32,      tipd_A32     );    w_34: VitalWireDelay (A33_ipd,      A33,      tipd_A33     );    w_35: VitalWireDelay (A34_ipd,      A34,      tipd_A34     );    w_36: VitalWireDelay (A35_ipd,      A35,      tipd_A35     );    w_37: VitalWireDelay (B0_ipd,       B0,       tipd_B0      );    w_38: VitalWireDelay (B1_ipd,       B1,       tipd_B1      );    w_39: VitalWireDelay (B2_ipd,       B2,       tipd_B2      );    w_40: VitalWireDelay (B3_ipd,       B3,       tipd_B3      );    w_41: VitalWireDelay (B4_ipd,       B4,       tipd_B4      );    w_42: VitalWireDelay (B5_ipd,       B5,       tipd_B5      );    w_43: VitalWireDelay (B6_ipd,       B6,       tipd_B6      );    w_44: VitalWireDelay (B7_ipd,       B7,       tipd_B7      );    w_45: VitalWireDelay (B8_ipd,       B8,       tipd_B8      );    w_46: VitalWireDelay (B9_ipd,       B9,       tipd_B9      );    w_47: VitalWireDelay (B10_ipd,      B10,      tipd_B10     );    w_48: VitalWireDelay (B11_ipd,      B11,      tipd_B11     );    w_49: VitalWireDelay (B12_ipd,      B12,      tipd_B12     );    w_50: VitalWireDelay (B13_ipd,      B13,      tipd_B13     );    w_51: VitalWireDelay (B14_ipd,      B14,      tipd_B14     );    w_52: VitalWireDelay (B15_ipd,      B15,      tipd_B15     );    w_53: VitalWireDelay (B16_ipd,      B16,      tipd_B16     );    w_54: VitalWireDelay (B17_ipd,      B17,      tipd_B17     );    w_55: VitalWireDelay (B18_ipd,      B18,      tipd_B18     );    w_56: VitalWireDelay (B19_ipd,      B19,      tipd_B19     );    w_57: VitalWireDelay (B20_ipd,      B20,      tipd_B20     );    w_58: VitalWireDelay (B21_ipd,      B21,      tipd_B21     );    w_59: VitalWireDelay (B22_ipd,      B22,      tipd_B22     );    w_60: VitalWireDelay (B23_ipd,      B23,      tipd_B23     );    w_61: VitalWireDelay (B24_ipd,      B24,      tipd_B24     );    w_62: VitalWireDelay (B25_ipd,      B25,      tipd_B25     );    w_63: VitalWireDelay (B26_ipd,      B26,      tipd_B26     );    w_64: VitalWireDelay (B27_ipd,      B27,      tipd_B27     );    w_65: VitalWireDelay (B28_ipd,      B28,      tipd_B28     );    w_66: VitalWireDelay (B29_ipd,      B29,      tipd_B29     );    w_67: VitalWireDelay (B30_ipd,      B30,      tipd_B30     );    w_68: VitalWireDelay (B31_ipd,      B31,      tipd_B31     );    w_69: VitalWireDelay (B32_ipd,      B32,      tipd_B32     );    w_70: VitalWireDelay (B33_ipd,      B33,      tipd_B33     );    w_71: VitalWireDelay (B34_ipd,      B34,      tipd_B34     );    w_72: VitalWireDelay (B35_ipd,      B35,      tipd_B35     );    w_73: VitalWireDelay (BENeg_ipd,    BENeg,    tipd_BENeg   );    w_74: VitalWireDelay (CLKA_ipd,     CLKA,     tipd_CLKA    );    w_75: VitalWireDelay (CLKB_ipd,     CLKB,     tipd_CLKB    );    w_76: VitalWireDelay (CSANeg_ipd,   CSANeg,   tipd_CSANeg  );    w_77: VitalWireDelay (CSBNeg_ipd,   CSBNeg,   tipd_CSBNeg  );    w_78: VitalWireDelay (ENA_ipd,      ENA,      tipd_ENA     );    w_79: VitalWireDelay (ENB_ipd,      ENB,      tipd_ENB     );    w_80: VitalWireDelay (FS0_ipd,      FS0,      tipd_FS0     );    w_81: VitalWireDelay (FS1_ipd,      FS1,      tipd_FS1     );    w_82: VitalWireDelay (MBA_ipd,      MBA,      tipd_MBA     );    w_83: VitalWireDelay (ODDEVEN_ipd,  ODDEVEN,  tipd_ODDEVEN );    w_84: VitalWireDelay (PGA_ipd,      PGA,      tipd_PGA     );    w_85: VitalWireDelay (PGB_ipd,      PGB,      tipd_PGB     );    w_86: VitalWireDelay (RSTNeg_ipd,   RSTNeg,   tipd_RSTNeg  );    w_87: VitalWireDelay (SIZ0_ipd,     SIZ0,     tipd_SIZ0    );    w_88: VitalWireDelay (SIZ1_ipd,     SIZ1,     tipd_SIZ1    );    w_89: VitalWireDelay (SW0_ipd,      SW0,      tipd_SW0     );    w_90: VitalWireDelay (SW1_ipd,      SW1,      tipd_SW1     );    w_91: VitalWireDelay (WRA_ipd,      WRA,      tipd_WRA     );    w_92: VitalWireDelay (WRB_ipd,      WRB,      tipd_WRB     );END BLOCK;---------------------------------------------------------------------------------- Main Behavior Block                                                        ----------------------------------------------------------------------------------  VITALBehavior: BLOCK    PORT (    A_ipd    : IN std_logic_vector(35 downto 0) := (OTHERS => 'X');     A        : OUT std_logic_vector(35 downto 0) := (OTHERS => 'U');     AEANeg   : OUT   std_logic := 'U';     AEBNeg   : OUT   std_logic := 'U';     AFANeg   : OUT   std_logic := 'U';     AFBNeg   : OUT   std_logic := 'U';     B_ipd    : IN std_logic_vector(35 downto 0) := (OTHERS => 'X');     B        : OUT std_logic_vector(35 downto 0) := (OTHERS => 'U');     BENeg    : IN    std_logic := 'X';     CLKA     : IN    std_logic := 'X';     CLKB     : IN    std_logic := 'X';     CSANeg   : IN    std_logic := 'X';     CSBNeg   : IN    std_logic := 'X';    EFANeg   : OUT   std_logic := 'U';     EFBNeg   : OUT   std_logic := 'U';     ENA      : IN    std_logic := 'X';     ENB      : IN    std_logic := 'X';    FFANeg   : OUT   std_logic := 'U';     FFBNeg   : OUT   std_logic := 'U';     FS0      : IN    std_logic := 'X';     FS1      : IN    std_logic := 'X';     MBA      : IN    std_logic := 'X';    MBF1Neg  : OUT   std_logic := 'U';    MBF2Neg  : OUT   std_logic := 'U';    ODDEVEN  : IN    std_logic := 'X';     PEFANeg  : OUT   std_logic := 'U';     PEFBNeg  : OUT   std_logic := 'U';     PGA      : IN    std_logic := 'X';     PGB      : IN    std_logic := 'X';     RSTNeg   : IN    std_logic := 'X';     SIZ0     : IN    std_logic := 'X';     SIZ1     : IN    std_logic := 'X';     SW0      : IN    std_logic := 'X';     SW1      : IN    std_logic := 'X';     WRA      : IN    std_logic := 'X';     WRB      : IN    std_logic := 'X'       );   PORT MAP (    A_ipd(0)    => A0_ipd,    A_ipd(1)    => A1_ipd,    A_ipd(2)    => A2_ipd,    A_ipd(3)    => A3_ipd,    A_ipd(4)    => A4_ipd,    A_ipd(5)    => A5_ipd,    A_ipd(6)    => A6_ipd,    A_ipd(7)    => A7_ipd,    A_ipd(8)    => A8_ipd,    A_ipd(9)    => A9_ipd,    A_ipd(10)   => A10_ipd,    A_ipd(11)   => A11_ipd,
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